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公开(公告)号：US20090153171A1
公开(公告)日：2009-06-18
申请号：US12314360
申请日：2008-12-09
Applicant: Sang-Sik Lee , Yun-Ha Park , Sung-Min Sim , Myoung-Sub Kim
Inventor： Sang-Sik Lee , Yun-Ha Park , Sung-Min Sim , Myoung-Sub Kim
IPC: G01R31/28
CPC classification number: G01R31/2874
Abstract: An apparatus for testing objects includes a test board having electrical connection areas to connect to the objects, a chamber fixture located on the test board to form test chambers that are configured to individually receive the objects, a thermoelectric element provided to each test chamber to adjust the temperature of the object, and a temperature controller for individually controlling operations of the thermoelectric elements.
Abstract translation: 一种用于测试物体的装置包括具有连接到物体的电气连接区域的测试板，位于测试板上的腔室夹具，以形成被配置为分别接收物体的测试室，设置到每个测试室的热电元件以调整 物体的温度和用于单独控制热电元件的操作的温度控制器。
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公开(公告)号：US20110312149A1
公开(公告)日：2011-12-22
申请号：US13036916
申请日：2011-02-28
Applicant: Heon Yong CHANG , Myoung Sub KIM , Gap Sok DO
Inventor： Heon Yong CHANG , Myoung Sub KIM , Gap Sok DO
IPC: H01L21/8239
CPC classification number: H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/128 , H01L45/144
Abstract: A phase change memory device includes a silicon substrate having a bar-type active region and an N-type impurity region formed in a surface of the active region. A first insulation layer is formed on the silicon substrate, and the first insulation layer includes a plurality of first contact holes and second contact holes. PN diodes are formed in the first contact holes. Heat sinks are formed in the first contact holes on the PN diodes, and contact plugs fill the second contact holes. A second insulation layer having third contact holes is formed on the first insulation layer. Heaters fill the third contact holes. A stack pattern of a phase change layer and a top electrode is formed to contact the heaters. The heat sink quickly cools heat transferred from the heater to the phase change layer.
Abstract translation: 相变存储器件包括具有棒状有源区和形成在有源区的表面中的N型杂质区的硅衬底。 第一绝缘层形成在硅衬底上，第一绝缘层包括多个第一接触孔和第二接触孔。 PN二极管形成在第一接触孔中。 在PN二极管上的第一接触孔中形成散热片，接触塞填充第二接触孔。 具有第三接触孔的第二绝缘层形成在第一绝缘层上。 加热器填充第三个接触孔。 形成相变层和顶部电极的堆叠图案以接触加热器。 散热片快速冷却从加热器传递到相变层的热量。
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公开(公告)号：US20090039333A1
公开(公告)日：2009-02-12
申请号：US12100536
申请日：2008-04-10
Applicant: Heon Yong CHANG , Myoung Sub KIM , Gap Sok DO
Inventor： Heon Yong CHANG , Myoung Sub KIM , Gap Sok DO
IPC: H01L45/00
CPC classification number: H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/128 , H01L45/144
Abstract: A phase change memory device includes a silicon substrate having a bar-type active region and an N-type impurity region formed in a surface of the active region. A first insulation layer is formed on the silicon substrate, and the first insulation layer includes a plurality of first contact holes and second contact holes. PN diodes are formed in the first contact holes. Heat sinks are formed in the first contact holes on the PN diodes, and contact plugs fill the second contact holes. A second insulation layer having third contact holes is formed on the first insulation layer. Heaters fill the third contact holes. A stack pattern of a phase change layer and a top electrode is formed to contact the heaters. The heat sink quickly cools heat transferred from the heater to the phase change layer.
Abstract translation: 相变存储器件包括具有棒状有源区和形成在有源区的表面中的N型杂质区的硅衬底。 第一绝缘层形成在硅衬底上，第一绝缘层包括多个第一接触孔和第二接触孔。 PN二极管形成在第一接触孔中。 在PN二极管上的第一接触孔中形成散热片，接触塞填充第二接触孔。 具有第三接触孔的第二绝缘层形成在第一绝缘层上。 加热器填充第三个接触孔。 形成相变层和顶部电极的堆叠图案以接触加热器。 散热片快速冷却从加热器传递到相变层的热量。
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4.发明申请Probe card for test of semiconductor chips and method for test of semiconductor chips using the same 审中-公开用于半导体芯片测试的探针卡和使用其的半导体芯片的测试方法公开(公告)号：US20080164898A1
公开(公告)日：2008-07-10
申请号：US12005888
申请日：2007-12-28
Applicant: Sung-Hoon Bae , Jung-Hyeon Kim , Young-Soo An , Ho-Jeong Choi , Myoung-Sub Kim
Inventor： Sung-Hoon Bae , Jung-Hyeon Kim , Young-Soo An , Ho-Jeong Choi , Myoung-Sub Kim
IPC: G01R31/02
CPC classification number: G01R1/07385 , G01R1/07342
Abstract: There are provided a probe card for test of semiconductor chips and a method for testing semiconductor chips using the probe card. In implementing the probe card for electrically testing semiconductor chips, the probe blocks corresponding to multiple selected ones of the semiconductor chips on the wafer can be selected so that the selected semiconductor chips are EDS tested in a one-step process. As the selected semiconductor chips are EDS tested in a one-step process, equipment efficiency is improved, and statistical objectivity of data indicating characteristics of the wafer can be achieved.
Abstract translation: 提供了用于半导体芯片测试的探针卡和使用探针卡测试半导体芯片的方法。 在实现用于电测试半导体芯片的探针卡时，可以选择对应于晶片上的多个选定的半导体芯片的探针块，使得所选择的半导体芯片在一步法中进行EDS测试。 由于所选择的半导体芯片在一步法中进行了EDS测试，所以提高了设备效率，并且可以实现表示晶片特性的数据的统计客观性。
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Patent Agency Ranking
5.发明授权公开(公告)号：US06541290B1
公开(公告)日：2003-04-01
申请号：US09710231
申请日：2000-11-10
Applicant: Kwang-Kyu Bang , Sang-Gil Kim , Myoung-Sub Kim , Ho-Jeong Choi
Inventor： Kwang-Kyu Bang , Sang-Gil Kim , Myoung-Sub Kim , Ho-Jeong Choi
IPC: H01L2100
CPC classification number: H01L23/5258 , H01L2924/0002 , H01L2924/00
Abstract: A fuse layout structure in a laser fuse box of a semiconductor integrated circuit and a method for fabricating the same. In one embodiment of the invention, the fuse layout structure in a laser fuse box of the semiconductor integrated circuit comprises a plurality of fuses with the central regions thereof extending parallel to each other within the fuse box, and the central regions of the fuses being covered with an insulative protection layer. Thus, the fuse layout structure of the present invention occupies a minimum area in the chip while minimizing influences of the heat generated by fusing neighboring fuses.
Abstract translation: 半导体集成电路的激光熔丝盒中的保险丝布置结构及其制造方法。 在本发明的一个实施例中，半导体集成电路的激光熔丝盒中的熔丝布置结构包括多个保险丝，其中心区域在保险丝盒内彼此平行延伸，并且保险丝的中心区域被覆盖 具有绝缘保护层。 因此，本发明的保险丝布置结构占用了芯片中的最小面积，同时最小化了通过熔化相邻熔丝产生的热的影响。
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6.发明授权公开(公告)号：US06682959B2
公开(公告)日：2004-01-27
申请号：US10367556
申请日：2003-02-13
Applicant: Kwang-Kyu Bang , Sang-Gil Kim , Myoung-Sub Kim , Ho-Jeong Choi
Inventor： Kwang-Kyu Bang , Sang-Gil Kim , Myoung-Sub Kim , Ho-Jeong Choi
IPC: H01L2100
CPC classification number: H01L23/5258 , H01L2924/0002 , H01L2924/00
Abstract: The invention relates to a fuse layout structure in a laser fuse box of a semiconductor integrated circuit and a method for fabricating the same. In one example of the invention, the fuse layout structure in a laser fuse box of the semiconductor integrated circuit includes a plurality of fuses with the central regions thereof extending parallel to each other within the fuse box, and the central regions of the fuses being covered with an insulative protection layer. Thus, the fuse layout structure of the present invention occupies a minimum area in the chip while minimizing influences of the heat generated by fusing neighboring fuses.
Abstract translation: 本发明涉及半导体集成电路的激光熔丝盒中的保险丝布置结构及其制造方法。 在本发明的一个示例中，半导体集成电路的激光熔丝盒中的熔丝布置结构包括多个保险丝，其中心区域在保险丝盒内彼此平行延伸，并且保险丝的中心区域被覆盖 具有绝缘保护层。 因此，本发明的保险丝布置结构占用了芯片中的最小面积，同时最小化了通过熔化相邻熔丝产生的热的影响。
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公开(公告)号：US08693241B2
公开(公告)日：2014-04-08
申请号：US13244181
申请日：2011-09-23
Applicant: Myoung Sub Kim , Soo Gil Kim , Nam Kyun Park , Sung Cheoul Kim , Gap Sok Do , Joon Seop Sim , Hyun Jeong Lee
Inventor： Myoung Sub Kim , Soo Gil Kim , Nam Kyun Park , Sung Cheoul Kim , Gap Sok Do , Joon Seop Sim , Hyun Jeong Lee
IPC: G11C11/00
CPC classification number: H01L45/1675 , G11C13/0004 , G11C2013/008 , G11C2213/71 , H01L27/2409 , H01L27/249 , H01L45/06 , H01L45/1226 , H01L45/1246 , H01L45/126 , H01L45/144
Abstract: A semiconductor integrated circuit device, a method of manufacturing the same, and a method of driving the same are provided. The device includes a semiconductor substrate, an upper electrode extending from a surface of the semiconductor substrate; a plurality of switching structures extending from both sidewalls of the upper electrode in a direction parallel to the surface of the semiconductor substrate, and a phase-change material layer disposed between the plurality of switching structures and the upper electrode.
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公开(公告)号：US08416616B2
公开(公告)日：2013-04-09
申请号：US13036916
申请日：2011-02-28
Applicant: Heon Yong Chang , Myoung Sub Kim , Gap Sok Do
Inventor： Heon Yong Chang , Myoung Sub Kim , Gap Sok Do
IPC: G11C11/00
CPC classification number: H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/128 , H01L45/144
Abstract: A phase change memory device includes a silicon substrate having a bar-type active region and an N-type impurity region formed in a surface of the active region. A first insulation layer is formed on the silicon substrate, and the first insulation layer includes a plurality of first contact holes and second contact holes. PN diodes are formed in the first contact holes. Heat sinks are formed in the first contact holes on the PN diodes, and contact plugs fill the second contact holes. A second insulation layer having third contact holes is formed on the first insulation layer. Heaters fill the third contact holes. A stack pattern of a phase change layer and a top electrode is formed to contact the heaters. The heat sink quickly cools heat transferred from the heater to the phase change layer.
Abstract translation: 相变存储器件包括具有棒状有源区和形成在有源区的表面中的N型杂质区的硅衬底。 第一绝缘层形成在硅衬底上，第一绝缘层包括多个第一接触孔和第二接触孔。 PN二极管形成在第一接触孔中。 在PN二极管上的第一接触孔中形成散热片，接触塞填充第二接触孔。 具有第三接触孔的第二绝缘层形成在第一绝缘层上。 加热器填充第三个接触孔。 形成相变层和顶部电极的堆叠图案以接触加热器。 散热片快速冷却从加热器传递到相变层的热量。
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9.发明申请公开(公告)号：US20130016555A1
公开(公告)日：2013-01-17
申请号：US13244181
申请日：2011-09-23
Applicant: Myoung Sub KIM , Soo Gil Kim , Nam Kyun Park , Sung Cheoul Kim , Gap Sok Do , Joon Seop Sim , Hyun Jeong Lee
Inventor： Myoung Sub KIM , Soo Gil Kim , Nam Kyun Park , Sung Cheoul Kim , Gap Sok Do , Joon Seop Sim , Hyun Jeong Lee
CPC classification number: H01L45/1675 , G11C13/0004 , G11C2013/008 , G11C2213/71 , H01L27/2409 , H01L27/249 , H01L45/06 , H01L45/1226 , H01L45/1246 , H01L45/126 , H01L45/144
Abstract: A semiconductor integrated circuit device, a method of manufacturing the same, and a method of driving the same are provided. The device includes a semiconductor substrate, an upper electrode extending from a surface of the semiconductor substrate; a plurality of switching structures extending from both sidewalls of the upper electrode in a direction parallel to the surface of the semiconductor substrate, and a phase-change material layer disposed between the plurality of switching structures and the upper electrode.
Abstract translation: 提供了一种半导体集成电路器件及其制造方法及其驱动方法。 该器件包括半导体衬底，从半导体衬底的表面延伸的上电极; 多个开关结构，其从与上述半导体基板的表面平行的方向从上述电极的两侧延伸;以及相变材料层，设置在上述多个开关结构体和上部电极之间。
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