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15 条记录 (耗时 0.023 秒)

    Architecture of laser fuse box of semiconductor integrated circuit and method for fabricating the same
    1.
    发明授权
    Architecture of laser fuse box of semiconductor integrated circuit and method for fabricating the same 有权
    半导体集成电路的激光熔丝盒结构及其制造方法

    公开(公告)号：US06682959B2

    公开(公告)日：2004-01-27

    申请号：US10367556

    申请日：2003-02-13

    申请人： Kwang-Kyu Bang ,  Sang-Gil Kim ,  Myoung-Sub Kim ,  Ho-Jeong Choi

    发明人： Kwang-Kyu Bang ,  Sang-Gil Kim ,  Myoung-Sub Kim ,  Ho-Jeong Choi

    IPC分类号： H01L2100

    CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The invention relates to a fuse layout structure in a laser fuse box of a semiconductor integrated circuit and a method for fabricating the same. In one example of the invention, the fuse layout structure in a laser fuse box of the semiconductor integrated circuit includes a plurality of fuses with the central regions thereof extending parallel to each other within the fuse box, and the central regions of the fuses being covered with an insulative protection layer. Thus, the fuse layout structure of the present invention occupies a minimum area in the chip while minimizing influences of the heat generated by fusing neighboring fuses.

    摘要翻译： 本发明涉及半导体集成电路的激光熔丝盒中的保险丝布置结构及其制造方法。 在本发明的一个示例中，半导体集成电路的激光熔丝盒中的熔丝布置结构包括多个保险丝，其中心区域在保险丝盒内彼此平行延伸，并且保险丝的中心区域被覆盖 具有绝缘保护层。 因此，本发明的保险丝布置结构占用了芯片中的最小面积，同时最小化了通过熔化相邻熔丝产生的热的影响。

    Architecture of laser fuse box of semiconductor integrated circuit and method for fabricating the same
    2.
    发明授权
    Architecture of laser fuse box of semiconductor integrated circuit and method for fabricating the same 有权
    半导体集成电路的激光熔丝盒结构及其制造方法

    公开(公告)号：US06541290B1

    公开(公告)日：2003-04-01

    申请号：US09710231

    申请日：2000-11-10

    申请人： Kwang-Kyu Bang ,  Sang-Gil Kim ,  Myoung-Sub Kim ,  Ho-Jeong Choi

    发明人： Kwang-Kyu Bang ,  Sang-Gil Kim ,  Myoung-Sub Kim ,  Ho-Jeong Choi

    IPC分类号： H01L2100

    CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A fuse layout structure in a laser fuse box of a semiconductor integrated circuit and a method for fabricating the same. In one embodiment of the invention, the fuse layout structure in a laser fuse box of the semiconductor integrated circuit comprises a plurality of fuses with the central regions thereof extending parallel to each other within the fuse box, and the central regions of the fuses being covered with an insulative protection layer. Thus, the fuse layout structure of the present invention occupies a minimum area in the chip while minimizing influences of the heat generated by fusing neighboring fuses.

    摘要翻译： 半导体集成电路的激光熔丝盒中的保险丝布置结构及其制造方法。 在本发明的一个实施例中，半导体集成电路的激光熔丝盒中的熔丝布置结构包括多个保险丝，其中心区域在保险丝盒内彼此平行延伸，并且保险丝的中心区域被覆盖 具有绝缘保护层。 因此，本发明的保险丝布置结构占用了芯片中的最小面积，同时最小化了通过熔化相邻熔丝产生的热的影响。

    Fuse box including make-link and redundant address decoder having the same, and method for repairing defective memory cell
    5.
    发明授权
    Fuse box including make-link and redundant address decoder having the same, and method for repairing defective memory cell 失效
    包括制造链路和具有相同功能的冗余地址解码器的保险丝盒以及用于修复有缺陷的存储器单元的方法

    公开(公告)号：US06850450B2

    公开(公告)日：2005-02-01

    申请号：US10075568

    申请日：2002-02-13

    申请人： Kwang-kyu Bang ,  Kyeong-seon Shin ,  Sang-seok Kang ,  Hyen-wook Ju ,  Jeong-ho Bang ,  Ho-Jeong Choi

    发明人： Kwang-kyu Bang ,  Kyeong-seon Shin ,  Sang-seok Kang ,  Hyen-wook Ju ,  Jeong-ho Bang ,  Ho-Jeong Choi

    IPC分类号： G11C29/00 ,  G11C11/00

    CPC分类号： G11C29/785 ,  G11C29/781

    摘要： A fuse box including make-links and a redundancy address decoder including the fuse box are provided. It is preferable that the fuse box includes a plurality of make-links for programming an address of a defective normal memory cell with an address of a corresponding redundant memory cell, and the address is a row address or a column address. The redundant address decoder includes a fuse box having a plurality of make-links for decoding an address of a defect cell and a redundant word line selection circuit for selecting a word line of a redundant cell corresponding to the address of the defect cell in response to a signal output from the fuse box.

    摘要翻译： 提供包括制造链路的保险丝盒和包括保险丝盒的冗余地址解码器。 优选地，保险丝盒包括多个制造链接，用于通过对应的冗余存储器单元的地址对有缺陷的正常存储器单元的地址进行编程，并且该地址是行地址或列地址。 冗余地址解码器包括具有用于对缺陷单元的地址进行解码的多个制造链路的熔丝盒和冗余字线选择电路，用于响应于对应于缺陷单元的地址的冗余单元的字线进行选择 从保险丝盒输出的信号。

    Probe card for test of semiconductor chips and method for test of semiconductor chips using the same
    6.
    发明申请
    Probe card for test of semiconductor chips and method for test of semiconductor chips using the same 审中-公开
    用于半导体芯片测试的探针卡和使用其的半导体芯片的测试方法

    公开(公告)号：US20080164898A1

    公开(公告)日：2008-07-10

    申请号：US12005888

    申请日：2007-12-28

    申请人： Sung-Hoon Bae ,  Jung-Hyeon Kim ,  Young-Soo An ,  Ho-Jeong Choi ,  Myoung-Sub Kim

    发明人： Sung-Hoon Bae ,  Jung-Hyeon Kim ,  Young-Soo An ,  Ho-Jeong Choi ,  Myoung-Sub Kim

    IPC分类号： G01R31/02

    CPC分类号： G01R1/07385 ,  G01R1/07342

    摘要： There are provided a probe card for test of semiconductor chips and a method for testing semiconductor chips using the probe card. In implementing the probe card for electrically testing semiconductor chips, the probe blocks corresponding to multiple selected ones of the semiconductor chips on the wafer can be selected so that the selected semiconductor chips are EDS tested in a one-step process. As the selected semiconductor chips are EDS tested in a one-step process, equipment efficiency is improved, and statistical objectivity of data indicating characteristics of the wafer can be achieved.

    摘要翻译： 提供了用于半导体芯片测试的探针卡和使用探针卡测试半导体芯片的方法。 在实现用于电测试半导体芯片的探针卡时，可以选择对应于晶片上的多个选定的半导体芯片的探针块，使得所选择的半导体芯片在一步法中进行EDS测试。 由于所选择的半导体芯片在一步法中进行了EDS测试，所以提高了设备​​效率，并且可以实现表示晶片特性的数据的统计客观性。

    Test socket
    7.
    发明申请
    Test socket 审中-公开
    测试插座

    公开(公告)号：US20090009204A1

    公开(公告)日：2009-01-08

    申请号：US12214932

    申请日：2008-06-24

    申请人： Sang-Sik Lee ,  Bo-Woo Kim ,  Ho-Jeong Choi

    发明人： Sang-Sik Lee ,  Bo-Woo Kim ,  Ho-Jeong Choi

    IPC分类号： G01R31/02

    CPC分类号： G01R1/0458 ,  G01R31/2875

    摘要： A test socket in accordance with one aspect of the present invention includes a socket body, a thermoelectric element and a heat transfer member. The socket body receives an object. The thermoelectric element is arranged in the socket body to emit heat and absorb heat in accordance with current directions. The heat transfer member is arranged between the object and the thermoelectric element to transfer a heat generated from the object to the thermoelectric element. Thus, the object may be directly provided with a desired test temperature using the thermoelectric element so that the desired test temperature may be set rapidly and accurately. Further, the heat transfer member interposed between the object and the thermoelectric element may quickly dissipate the heat in the object.

    摘要翻译： 根据本发明的一个方面的测试插座包括插座体，热电元件和传热构件。 插座主体接收一个对象。 热电元件布置在插座主体中以发射热量并根据电流方向吸收热量。 传热构件设置在物体和热电元件之间，以将从物体产生的热量传递到热电元件。 因此，可以使用热电元件将物体直接设置有期望的测试温度，使得可以快速且准确地设置期望的测试温度。 此外，介于物体和热电元件之间的传热构件可能会快速地散发物体中的热量。

    Method of testing a semiconductor chip and jig used in the method
    8.
    发明授权
    Method of testing a semiconductor chip and jig used in the method 失效
    在该方法中使用的半导体芯片和夹具的测试方法

    公开(公告)号：US07323891B2

    公开(公告)日：2008-01-29

    申请号：US11420205

    申请日：2006-05-24

    申请人： Dae-Jong Kim ,  Ho-Jeong Choi ,  Chan-Soon Park

    发明人： Dae-Jong Kim ,  Ho-Jeong Choi ,  Chan-Soon Park

    IPC分类号： G01R31/02

    CPC分类号： G01R31/311 ,  G01R31/2831 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/00

    摘要： A method of and testing jig for sequentially testing front and rear surfaces of a semiconductor chip is shown. The testing jig includes a support package having a first cavity over which the semiconductor chip mounts; an infrared filter affixed relative to the first cavity and attached to a rear surface of the semiconductor chip; and a test substrate having a second cavity exposing the infrared filter and upon which the support package mounts. Front and rear surfaces of the semiconductor chip can be conveniently and sequentially tested. Because the testing jig includes the infrared filter and the heat pad, heat can be easily transmitted to the defective chip.

    摘要翻译： 示出了用于顺序测试半导体芯片的前表面和后表面的方法和测试夹具。 测试夹具包括具有半导体芯片安装在其上的第一空腔的支撑封装; 相对于所述第一空腔固定并附着到所述半导体芯片的后表面的红外滤光器; 以及具有暴露所述红外滤光器的第二腔的测试衬底，并且所述支撑封装安装在所述衬底上。 半导体芯片的前表面和后表面可以方便且顺序地测试。 由于测试夹具包括红外线过滤器和加热垫，所以热量可以很容易地传递到有缺陷的芯片。

    System and method for testing semiconductor integrated circuit in parallel
    9.
    发明申请
    System and method for testing semiconductor integrated circuit in parallel 审中-公开
    半导体集成电路并行测试的系统和方法

    公开(公告)号：US20080164894A1

    公开(公告)日：2008-07-10

    申请号：US12006560

    申请日：2008-01-03

    申请人： Min-Gu Kim ,  Young-Soo An ,  Ho-Jeong Choi ,  Jung-Hyeon Kim

    发明人： Min-Gu Kim ,  Young-Soo An ,  Ho-Jeong Choi ,  Jung-Hyeon Kim

    IPC分类号： G01R31/26

    CPC分类号： G01R31/2886 ,  G01R31/2889

    摘要： A system and method for testing a semiconductor integrated circuit (IC) in parallel includes a probe chuck, a test head, and a test controller. The probe chuck loads a plurality of different types of semiconductor DUTs. The test head provides a plurality of circuit sites to independently and simultaneously test the different types of semiconductor DUTs, and the test controller controls the test head and the probe chuck.

    摘要翻译： 用于同时测试半导体集成电路（IC）的系统和方法包括探针卡盘，测试头和测试控制器。 探头卡盘装载多种不同类型的半导体DUT。 测试头提供多个电路位置，以独立并同时测试不同类型的半导体DUT，并且测试控制器控制测试头和探头卡盘。

    Multilayer type test board assembly for high-precision inspection
    10.
    发明授权
    Multilayer type test board assembly for high-precision inspection 有权
    多层型测试板组件进行高精度检测

    公开(公告)号：US07786721B2

    公开(公告)日：2010-08-31

    申请号：US12006543

    申请日：2008-01-03

    申请人： Min-Gu Kim ,  Young-Soo An ,  Ho-Jeong Choi ,  Jung-Hyeon Kim

    发明人： Min-Gu Kim ,  Young-Soo An ,  Ho-Jeong Choi ,  Jung-Hyeon Kim

    IPC分类号： G01R31/28 ,  G01R31/26

    CPC分类号： G01R31/2851 ,  G01R1/04 ,  H05K1/144 ,  H05K1/148 ,  H05K2201/042 ,  H05K2201/09972 ,  H05K2201/10371

    摘要： There is provided a multilayer type test board assembly for high-precision inspection. The multilayer test board assembly comprises: a plurality of test boards separated from each other according to their functions, having input/output signal terminals, and including at least one test board each having a first section where first mounting devices sensitive to an influence of electrical signals are mounted and a second section where second mounting devices insensitive to an influence of electrical signals are mounted; spacers that arrange the test boards in parallel by spacing apart the test boards by predetermined intervals; connection cables connected to the input/output signal terminals of the test boards; and a signal shielding fence formed on each of the at least one test board so as to protect the first mounting devices from electrical signals generated by the second mounting devices.

    摘要翻译： 提供了一种用于高精度检测的多层型测试板组件。 多层测试板组件包括：根据功能彼此分离的多个测试板，具有输入/输出信号端子，并且包括至少一个测试板，每个测试板具有第一部分，其中第一安装装置对电气的影响敏感 信号被安装，并且第二部分安装对电信号的影响不敏感的第二安装装置; 间隔件通过以预定的间隔隔开测试板来平行布置测试板; 连接电缆连接到测试板的输入/输出信号端子; 以及形成在所述至少一个测试板中的每一个上的信号屏蔽栅栏，以便保护所述第一安装装置免受由所述第二安装装置产生的电信号。