公开(公告)号：US08642442B2

公开(公告)日：2014-02-04

申请号：US12869569

申请日：2010-08-26

申请人： Nam-Kyeong Kim ,  Jeong-Min Choi

发明人： Nam-Kyeong Kim ,  Jeong-Min Choi

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11517 ,  G11C16/0408 ,  G11C16/0441 ,  G11C16/10 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

摘要： Subject matter disclosed herein relates to a memory device, and more particularly to a nonvolatile memory device having a recess structure and methods of fabricating same.

公开(公告)号：US08268685B2

公开(公告)日：2012-09-18

申请号：US13069273

申请日：2011-03-22

申请人： Jae Chul Om ,  Nam Kyeong Kim ,  Se Jun Kim

发明人： Jae Chul Om ,  Nam Kyeong Kim ,  Se Jun Kim

IPC分类号： H01L21/336

CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/66825

摘要： A NAND flash memory device and method of manufacturing the same is disclosed. Source and drain select transistor gates are recessed lower than an active region of a semiconductor substrate. A valid channel length of the source and drain select transistor gates is longer than a channel length of memory cell gates. Accordingly, an electric field between a source region and a drain region of the select transistor can be reduced. It is thus possible to prevent program disturbance from occurring in edge memory cells adjacent to the source and drain select transistors in non-selected cell strings.

摘要翻译： 公开了NAND​​闪速存储器件及其制造方法。 源极和漏极选择晶体管栅极比半导体衬底的有源区域低。 源极和漏极选择晶体管栅极的有效沟道长度比存储器单元栅极的沟道长度长。 因此，可以减小选择晶体管的源极区域和漏极区域之间的电场。 因此，可以防止在非选择的单元串中与源极和漏极选择晶体管相邻的边缘存储单元中发生程序干扰。

公开(公告)号：US20100200902A1

公开(公告)日：2010-08-12

申请号：US12762778

申请日：2010-04-19

申请人： Jae Chul Om ,  Nam Kyeong Kim

发明人： Jae Chul Om ,  Nam Kyeong Kim

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L29/66621

摘要： A method of manufacturing a NAND flash memory device. A semiconductor substrate of a portion in which a source select line SSL and a drain select line DSL will be formed is recessed selectively or entirely to a predetermined depth. Accordingly, the channel length of a gate can be increased and disturbance can be reduced. It is therefore possible to improve the reliability and yield of devices.

摘要翻译： 一种制造NAND闪速存储器件的方法。 其中将形成源极选择线SSL和漏极选择线DSL的部分的半导体衬底被选择性地或完全地凹入到预定深度。 因此，可以增加栅极的沟道长度并减小干扰。 因此可以提高装置的可靠性和产量。

公开(公告)号：US20080298127A1

公开(公告)日：2008-12-04

申请号：US11965191

申请日：2007-12-27

申请人： Nam Kyeong Kim ,  Ju Yeab Lee ,  Keum Hwan Noh

发明人： Nam Kyeong Kim ,  Ju Yeab Lee ,  Keum Hwan Noh

IPC分类号： G11C16/26

CPC分类号： G11C16/3418 ,  G11C16/0483 ,  G11C16/3427

摘要： Provided is a method of reading a flash memory device for depressing read disturb. According to the method, a first voltage is applied to a gate of the drain select transistor to turn on the drain select transistor, and a read voltage is applied to a gate of a selected transistor among the plurality of memory cells. Then, a pass voltage is applied to gates of unselected transistors among the plurality of memory cells. Furthermore, when the pass voltage is applied, a first pass voltage is applied and then a second pass voltage is applied after an elapse of a predetermined time following the applying of the first pass voltage. The second pass voltage has a level different from that of the first pass voltage.

摘要翻译： 提供了一种读取用于按下读取干扰的闪速存储器件的方法。 根据该方法，将第一电压施加到漏极选择晶体管的栅极以使漏极选择晶体管导通，并且将读取电压施加到多个存储单元中的选定晶体管的栅极。 然后，对多个存储单元中的未选择晶体管的栅极施加通过电压。 此外，当施加通过电压时，施加第一通过电压，然后在施加第一通过电压之后经过预定时间之后施加第二通过电压。 第二通过电压具有与第一通过电压不同的电平。

公开(公告)号：US20070207580A1

公开(公告)日：2007-09-06

申请号：US11618702

申请日：2006-12-29

申请人： Sun Mi Park ,  Yoo Nam Jeon ,  Nam Kyeong Kim ,  Se Jun Kim

发明人： Sun Mi Park ,  Yoo Nam Jeon ,  Nam Kyeong Kim ,  Se Jun Kim

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  H01L21/76849 ,  H01L21/76877 ,  H01L27/11521

摘要： A method of manufacturing a flash memory device includes etching an insulating layer provided over a substrate to form a contact hole to define a contact hole exposing a junction region formed on the substrate. The contact hole is filled with a first conductive material, the first conductive material contacting the junction region and extending above an upper surface of the contact hole. The first conductive material is etched to partly fill the contact hole, so that the first conductive material fills a lower portion of the contact hole, wherein an upper portion of the contact hole remains not filled due to the etching of the first conductive material, wherein the etched first conductive material defines a contact plug. A first dielectric layer and a second dielectric layer are formed over the contact plug, thereby filling the upper portion of the contact hole. Part of the first and second dielectric layers is etched to expose the contact plug and the upper portion of the contact hole. A second conductive material is formed on the contact plug and filling the upper portion of the contact hole to form a bit line.

摘要翻译： 制造闪速存储器件的方法包括蚀刻设置在衬底上的绝缘层以形成接触孔，以限定暴露形成在衬底上的接合区域的接触孔。 接触孔填充有第一导电材料，第一导电材料接触接合区并在接触孔的上表面上方延伸。 第一导电材料被蚀刻以部分地填充接触孔，使得第一导电材料填充接触孔的下部，其中接触孔的上部部分由于蚀刻第一导电材料而保持未填充，其中 蚀刻的第一导电材料限定接触插塞。 第一电介质层和第二电介质层形成在接触插塞上，从而填充接触孔的上部。 蚀刻第一和第二电介质层的一部分以暴露接触插塞和接触孔的上部。 第二导电材料形成在接触插塞上并填充接触孔的上部以形成位线。

公开(公告)号：US20050006683A1

公开(公告)日：2005-01-13

申请号：US10899171

申请日：2004-07-27

申请人： Nam-Kyeong Kim ,  Soon-Yong Kweon ,  Seung-Jin Yeom

发明人： Nam-Kyeong Kim ,  Soon-Yong Kweon ,  Seung-Jin Yeom

IPC分类号： H01L27/105 ,  H01L21/02 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/76

CPC分类号： H01L27/11502 ,  H01L27/11507 ,  H01L28/56

摘要： The present invention provides a ferroelectric memory device capable of suppressing a defect generation due to a charge impact and a method for fabricating the same. The ferroelectric memory device includes: a semiconductor substrate on which a transistor is formed; a semiconductor substrate structure having a transistor; a lower electrode formed on an interfacial insulation layer and connected to a source/drain region of the transistor; an isolating insulation layer on the interfacial insulation layer; a ferroelectric layer covering the isolating insulation layer and lower electrode; an oxygen vacancy compensation layer being formed on the ferroelectric layer and compensating an oxygen vacancy caused by deoxidization of a composition of the ferroelectric layer; and an upper electrode formed on the oxygen vacancy compensation layer.

摘要翻译： 本发明提供能够抑制由电荷冲击引起的缺陷产生的铁电存储器件及其制造方法。 铁电存储器件包括：形成晶体管的半导体衬底; 具有晶体管的半导体衬底结构; 形成在界面绝缘层上并连接到晶体管的源/漏区的下电极; 界面绝缘层上的隔离绝缘层; 覆盖隔离绝缘层和下电极的铁电层; 在所述铁电层上形成氧空位补偿层，并且补偿由所述铁电层的组合物脱氧引起的氧空位; 以及形成在氧空位补偿层上的上电极。

公开(公告)号：US06747302B2

公开(公告)日：2004-06-08

申请号：US10133505

申请日：2002-04-26

申请人： Nam-Kyeong Kim ,  Seung-Jin Yeom ,  Woo-Seok Yang ,  Soon-Yong Kweon

发明人： Nam-Kyeong Kim ,  Seung-Jin Yeom ,  Woo-Seok Yang ,  Soon-Yong Kweon

IPC分类号： H01L2100

CPC分类号： H01L21/02197 ,  H01L21/02266 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/02282 ,  H01L21/02356 ,  H01L21/31691 ,  H01L28/55

摘要： A ferroelectric memory device and a method for manufacturing the same is disclosed. Because a (BixLay)Ti3O12 (BLT) layer, which can be crystallized in relatively low temperature, is used in a capacitor, the electrical characteristics of the ferroelectric capacitor can be improved. The method for manufacturing ferroelectric memory device includes the steps of forming a first conductive layer for a bottom electrode on a semiconductor substrate, forming the (BixLay)Ti3O12 ferroelectric layer, wherein ‘x’ representing atomic concentration of Bi ranges from about 3.25 to about 3.35 and ‘y’ representing atomic concentration of La ranges from about 0.70 to about 0.90 and forming a second conductive layer for a top electrode on the (BixLay)Ti3O12 ferroelectric layer.

摘要翻译： 公开了铁电存储器件及其制造方法。 因为可以在较低温度下结晶的（BixLay）Ti 3 O 12（BLT）层用于电容器中，因此可以提高铁电电容器的电特性。 制造铁电存储器件的方法包括以下步骤：在半导体衬底上形成用于底部电极的第一导电层，形成（BixLay）Ti 3 O 12铁电层，其中代表Bi的原子浓度的“x”范围为约3.25至约3.35 和表示La的原子浓度的“y”范围为约0.70至约0.90，并且在（BixLay）Ti 3 O 12铁电层上形成用于顶部电极的第二导电层。

公开(公告)号：US6063639A

公开(公告)日：2000-05-16

申请号：US429128

申请日：1999-10-28

申请人： Nam Kyeong Kim ,  Seung Jin Yeom

发明人： Nam Kyeong Kim ,  Seung Jin Yeom

IPC分类号： H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/00

CPC分类号： H01L28/55 ,  H01L21/02197 ,  H01L21/0223 ,  H01L21/02252 ,  H01L21/31691

摘要： A method for fabricating a ferroelectric capacitor of nonvolatile semiconductor memory device includes the steps of forming an amorphous layer on a resulting structure after performing a specific process, forming perovskite nuclei within the amorphous layer by an oxidation reaction in plasma atmosphere and performing a thermal process for growing the grains to form a ferroelectric thin film. The perovskite nuclei are formed at a low temperature, so that the ferroelectric capacitor has improved properties such as high density, high polarization and low leakage current.

摘要翻译： 一种制造非易失性半导体存储器件的铁电电容器的方法包括以下步骤：在进行特定工艺后在所得结构上形成非晶层，通过等离子体气氛中的氧化反应在非晶层内形成钙钛矿晶核，并进行热处理 生长晶粒形成铁电薄膜。 在低温下形成钙钛矿核，使铁电电容器具有改善的性能，如高密度，高极化和低漏电流。

公开(公告)号：US07944758B2

公开(公告)日：2011-05-17

申请号：US12492446

申请日：2009-06-26

申请人： Nam-Kyeong Kim ,  Jung-Min Choi

发明人： Nam-Kyeong Kim ,  Jung-Min Choi

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/102 ,  G11C16/3418 ,  G11C16/3427

摘要： A method for performing a copy-back operation in a non-volatile memory device includes: measuring and recording a maximum program voltage used to program a part of target data to copy-back when a copy-back command is inputted; and performing a copy-back operation using the recorded maximum program voltage.

摘要翻译： 一种用于在非易失性存储装置中执行复制操作的方法包括：当输入复制命令时，测量和记录用于编程目标数据的一部分的最大编程电压以进行复制; 并使用记录的最大编程电压执行复制操作。

公开(公告)号：US20110070706A1

公开(公告)日：2011-03-24

申请号：US12956878

申请日：2010-11-30

申请人： Nam-Kyeong Kim ,  Won Sic Woo

发明人： Nam-Kyeong Kim ,  Won Sic Woo

IPC分类号： H01L21/336

CPC分类号： H01L27/11524 ,  H01L27/11521

摘要： A method for fabricating a NAND type flash memory device includes defining a select transistor region and a memory cell region in a semiconductor substrate, forming a tunnel insulating layer, a floating gate conductive layer, and a dielectric layer over a semiconductor substrate, etching the dielectric layer, thereby forming an opening exposing the floating gate conductive layer, forming a low resistance layer in the opening, forming a control gate conductive layer over the semiconductor substrate, and etching the control gate conductive layer, the dielectric layer, the floating gate conductive layer, and the tunnel insulating layer to form gate stacks of memory cells and source/drain select transistors.

摘要翻译： 一种制造NAND型闪速存储器件的方法包括在半导体衬底中限定选择晶体管区域和存储单元区域，在半导体衬底上形成隧道绝缘层，浮栅导电层和电介质层，蚀刻电介质 从而形成露出浮置栅极导电层的开口，在开口中形成低电阻层，在半导体衬底上形成控制栅极导电层，并蚀刻控制栅极导电层，电介质层，浮置栅极导电层 和隧道绝缘层，以形成存储器单元和源极/漏极选择晶体管的栅极堆叠。