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    Early resolving instructions
    3.
    发明申请
    Early resolving instructions 有权
    早期解决说明

    公开(公告)号：US20050033941A1

    公开(公告)日：2005-02-10

    申请号：US10491944

    申请日：2002-10-07

    申请人： Nicholas Joyce ,  Nigel Topham

    发明人： Nicholas Joyce ,  Nigel Topham

    IPC分类号： G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3804 ,  G06F9/3867 ,  G06F9/3885

    摘要： Techniques are disclosed for handling control transfer instructions in pipelined processors. Such instructions may cause the sequence of subsequent instructions to change, and thus may require subsequent instructions to be deleted from the processor's pipeline. Pre-decode means (110) are provided for at least partially decoding control transfer instructions early in the pipeline. Subsequent instructions can then be prevented from progressing through the pipeline. The mechanism required to delete unwanted instructions is thereby simplified.

    摘要翻译： 公开了用于处理流水线处理器中的控制传送指令的技术。 这样的指令可能导致后续指令的顺序改变，因此可能需要从处理器的流水线中删除后续指令。 预解码装置（110）被提供用于在流水线的早期至少部分地解码控制传输指令。 随后可以防止随后的指令进入管道。 从而简化了删除不需要的指令所需的机制。

    Processor and method for generating and storing compressed instructions in a program memory and decompressed instructions in an instruction cache wherein the decompressed instructions are assigned imaginary addresses derived from information stored in the program memory with the compressed instructions
    5.
    发明申请
    Processor and method for generating and storing compressed instructions in a program memory and decompressed instructions in an instruction cache wherein the decompressed instructions are assigned imaginary addresses derived from information stored in the program memory with the compressed instructions 有权
    用于在程序存储器中生成和存储压缩指令的处理器和方法，以及指令高速缓存中的解压缩指令，其中解压缩指令被分配了从压缩指令存储在程序存储器中的信息导出的虚地址

    公开(公告)号：US20050125633A1

    公开(公告)日：2005-06-09

    申请号：US11035434

    申请日：2005-01-12

    申请人： Nigel Topham

    发明人： Nigel Topham

    IPC分类号： G06F12/08 ,  G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38

    CPC分类号： G06F9/3808 ,  G06F9/30178 ,  G06F9/325 ,  G06F9/3802 ,  G06F9/382 ,  G06F9/3853

    摘要： Instructions of a program are stored in compressed form in a program memory (12). In a processor which executes the instructions, a program counter (50) identifies a position in the program memory. An instruction cache (40) has cache blocks, each for storing one or more instructions of the program in decompressed form. A cache loading unit (42) includes a decompression section (44) and performs a cache loading operation in which one or more compressed-form instructions are read from the position in the program memory identified by the program counter and are decompressed and stored in one of the said cache blocks of the instruction cache. A cache pointer (52) identifies a position in the instruction cache of an instruction to be fetched for execution. An instruction fetching unit (46) fetches an instruction to be executed from the position identified by the cache pointer. When a cache miss occurs because the instruction to be fetched is not present in the instruction cache, the cache loading unit performs such a cache loading operation. An updating unit (48) updates the program counter and cache pointer in response to the fetching of instructions so as to ensure that the position identified by the said program counter is maintained consistently at the position in the program memory at which the instruction to be fetched from the instruction cache is stored in compressed form.

    摘要翻译： 程序的指令以压缩形式存储在程序存储器（12）中。 在执行指令的处理器中，程序计数器（50）识别程序存储器中的位置。 指令高速缓存（40）具有高速缓存块，每个缓存块用于以解压缩的形式存储程序的一个或多个指令。 高速缓存加载单元（42）包括解压缩部分（44），并且执行高速缓存加载操作，其中从程序计数器识别的程序存储器中的位置读取一个或多个压缩形式指令，并将其解压缩并存储在一个 的指令高速缓存的所述缓存块。 高速缓存指针（52）识别指令高速缓存中要获取的指令执行的位置。 指令取出单元（46）从由高速缓存指针识别的位置取出要执行的指令。 当由于要获取的指令不存在于指令高速缓存中而发生高速缓存未命中时，高速缓存加载单元执行这种高速缓存加载操作。 更新单元（48）响应于指令的取出来更新程序计数器和高速缓存指针，以便确保所述程序计数器识别的位置一致地保持在程序存储器中要获取的指令的位置 从指令缓存中以压缩形式存储。

    Systems and methods for performing branch prediction in a variable length instruction set microprocessor
    7.
    发明申请
    Systems and methods for performing branch prediction in a variable length instruction set microprocessor 审中-公开
    用于在可变长度指令集微处理器中执行分支预测的系统和方法

    公开(公告)号：US20050278517A1

    公开(公告)日：2005-12-15

    申请号：US11132428

    申请日：2005-05-19

    申请人： Kar-Lik Wong ,  James Hakewill ,  Nigel Topham ,  Rich Fuhler

    发明人： Kar-Lik Wong ,  James Hakewill ,  Nigel Topham ,  Rich Fuhler

    IPC分类号： G06F9/00 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F12/00 ,  G06F12/08 ,  G06F15/00 ,  G06F15/76 ,  G06F15/78 ,  H03M13/00

    CPC分类号： G06F9/3861 ,  G06F5/01 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30181 ,  G06F9/32 ,  G06F9/325 ,  G06F9/3802 ,  G06F9/3806 ,  G06F9/3816 ,  G06F9/3844 ,  G06F9/3846 ,  G06F9/3885 ,  G06F9/3897 ,  G06F11/3648 ,  G06F12/0802 ,  G06F15/7867 ,  Y02D10/12 ,  Y02D10/13

    摘要： A method of performing branch prediction in a microprocessor using variable length instructions is provided. An instruction is fetched from memory based on a specified fetch address and a branch prediction is made based on the address. The prediction is selectively discarded if the look-up was based on a non-sequential fetch to an unaligned instruction address and a branch target alignment cache (BTAC) bit of the instruction is equal to zero. In order to remove the inherent latency of branch prediction, an instruction prior to a branch instruction may be fetched concurrently with a branch prediction unit look-up table entry containing prediction information for a next instruction word. Then, the branch instruction is fetched and a prediction is made on this branch instruction based on information fetched in the previous cycle. The predicted target instruction is fetched on the next clock cycle. If zero overhead loops are used, a look-up table of a branch prediction unit is updated whenever the zero-overhead loop mechanism is updated. A last fetch address of a last instruction of a loop body of a zero overhead loop in the branch prediction look-up table is stored. Then, whenever an instruction fetch hits the end of a loop body, predictively re-directing an instruction fetch to the start of the loop body. The last fetch address of the loop body is derived from the address of the first instruction after the end of the loop.

    摘要翻译： 提供了一种使用可变长度指令在微处理器中执行分支预测的方法。 基于指定的提取地址从存储器取出指令，并且基于该地址进行分支预测。 如果查找是基于对非对齐指令地址的非顺序提取，并且指令的分支目标对准高速缓存（BTAC）位等于零，则有选择地丢弃该预测。 为了消除分支预测的固有等待时间，分支指令之前的指令可以与包含下一个指令字的预测信息的分支预测单元查找表条目同时取出。 然后，取出分支指令，并根据前一周期取得的信息，对该分支指令进行预测。 预测的目标指令在下一个时钟周期内获取。 如果使用零开销循环，则每当零开销循环机制被更新时，分支预测单元的查找表被更新。 存储分支预测查询表中零开销循环的循环体的最后指令的最后提取地址。 然后，每当指令提取命中循环体的结尾时，预先将指令重新指向循环体的开头。 循环体的最后一个获取地址是从循环结束后的第一个指令的地址导出的。

    Instruction sets for processors
    8.
    发明申请
    Instruction sets for processors 有权
    处理器指令集

    公开(公告)号：US20050223192A1

    公开(公告)日：2005-10-06

    申请号：US11147689

    申请日：2005-06-08

    申请人： Nigel Topham

    发明人： Nigel Topham

    IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/45

    CPC分类号： G06F9/3017 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3885

    摘要： A processor has respective first and second external instruction formats (F1, F2) in which instructions (add, load) are received by the processor. Each instruction has an opcode (e.g. 1011) which specifies an operation to be executed. Each external format has one or more preselected opcode bits (F1: i+1˜i+4; F2:i+1˜i+3) in which the opcode appears. The processor also has an internal instruction format (G1) into which instructions in the external formats are translated prior to execution of the operation. A first operation (add) is specifiable in both the first and second external formats (F1, F2) and a second operation (load) is specifiable in the second external format (F2). The first and second operations have distinct opcodes (101, 011) in the second external format. In each of the preselected opcode bits which the first and second external formats have in common (i+1˜i+3), the opcodes of the first operation (101) in the two external formats are identical. Such “congruent” instruction encodings can enable a translation process, for translating the external-format opcode into a corresponding internal-format opcode, to be carried out simply and quickly without the need to positively identify each individual external-format opcode.

    摘要翻译： 处理器具有其中处理器接收到指令（加载，加载）的相应的第一和第二外部指令格式（F 1，F 2，2）。 每个指令具有指定要执行的操作的操作码（例如1011）。 每个外部格式具有一个或多个预先选择的操作码位（F 1> 1：i + 1〜i + 4; F 2 2：i + 1〜i + 3），其中 操作码出现。 处理器还具有在执行操作之前将外部格式的指令转换到的内部指令格式（G <1> 1 ）。 第一操作（添加）可以在第一和第二外部格式（F 1 1，F 2 2）中被指定，并且第二操作（加载）可以在第二外部格式 格式（F> 2 ）。 第一和第二操作在第二外部格式中具有不同的操作码（101,011）。 在第一和第二外部格式具有共同（i + 1〜i + 3）的每个预选操作码位中，两种外部格式的第一操作（101）的操作码是相同的。 这种“一致”指令编码可以实现翻译过程，将外部格式操作码转换为相应的内部格式操作码，以便简单快速地执行，而无需积极地识别每个单独的外部格式操作码。