公开(公告)号：US20100181673A1

公开(公告)日：2010-07-22

申请号：US12652204

申请日：2010-01-05

申请人： Yumi HAYASHI ,  Atsuko Sakata ,  Kei Watanabe ,  Noriaki Matsunaga ,  Shinichi Nakao ,  Makoto Wada ,  Hiroshi Toyoda

发明人： Yumi HAYASHI ,  Atsuko Sakata ,  Kei Watanabe ,  Noriaki Matsunaga ,  Shinichi Nakao ,  Makoto Wada ,  Hiroshi Toyoda

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L23/485 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a first film containing a metal whose energy for forming silicide thereof is lower than that of Cu silicide inside the opening; forming a second film that is conductive and contains copper (Cu) in the opening in which the first film containing the metal is formed; and forming a compound film containing Cu and silicon (Si) selectively on the second film in an atmosphere in which a temperature of the substrate is below 300° C.

摘要翻译： 一种制造半导体器件的方法，包括在衬底上形成电介质膜; 在电介质膜中形成开口; 形成含有其形成硅化物的能量低于开口内的硅化铜的能量的金属的第一膜; 在形成有含有金属的第一膜的开口中形成导电性并且含有铜（Cu）的第二膜; 以及在所述基板的温度低于300℃的气氛中，在所述第二膜上选择性地形成含有Cu和硅（Si）的复合膜。

公开(公告)号：US20130093090A1

公开(公告)日：2013-04-18

申请号：US13707359

申请日：2012-12-06

申请人： Yumi HAYASHI ,  Atsuko Sakata ,  Kei Watanabe ,  Noriaki Matsunaga ,  Shinichi Nakao ,  Makoto Wada ,  Hiroshi Toyoda

发明人： Yumi HAYASHI ,  Atsuko Sakata ,  Kei Watanabe ,  Noriaki Matsunaga ,  Shinichi Nakao ,  Makoto Wada ,  Hiroshi Toyoda

IPC分类号： H01L23/485

CPC分类号： H01L23/485 ,  H01L21/76814 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76856 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76886 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for fabricating a semiconductor device, includes forming a dielectric film above a substrate; forming an opening in the dielectric film; forming a first film containing a metal whose energy for forming silicide thereof is lower than that of Cu silicide inside the opening; forming a second film that is conductive and contains copper (Cu) in the opening in which the first film containing the metal is formed; and forming a compound film containing Cu and silicon (Si) selectively on the second film in an atmosphere in which a temperature of the substrate is below 300° C.

摘要翻译： 一种制造半导体器件的方法，包括在衬底上形成电介质膜; 在电介质膜中形成开口; 形成含有其形成硅化物的能量低于开口内的硅化铜的能量的金属的第一膜; 在形成有含有金属的第一膜的开口中形成导电性并且含有铜（Cu）的第二膜; 以及在所述基板的温度低于300℃的气氛中，在所述第二膜上选择性地形成含有Cu和硅（Si）的复合膜。

公开(公告)号：US20090283913A1

公开(公告)日：2009-11-19

申请号：US12435485

申请日：2009-05-05

申请人： Yumi HAYASHI ,  Noriaki Matsunaga ,  Takamasa Usui

发明人： Yumi HAYASHI ,  Noriaki Matsunaga ,  Takamasa Usui

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76846 ,  H01L21/76847 ,  H01L21/76849 ,  H01L21/76867 ,  H01L21/76877 ,  H01L21/76886 ,  H01L21/76888 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes: a copper (Cu) wire having a first region and a second region in which densities of silicon (Si) and oxygen (O) atoms are higher than in the first region; a compound film that is selectively formed on the Cu wire and contains Cu and Si; and a dielectric film formed on a side surface side of the Cu wire.

摘要翻译： 半导体器件包括：铜（Cu）线，其具有第一区域和第二区域，其中硅（Si）和氧（O）原子的密度高于第一区域; 选择性地形成在Cu线上并含有Cu和Si的复合膜; 以及形成在Cu线的侧面侧的电介质膜。

公开(公告)号：US20120187569A1

公开(公告)日：2012-07-26

申请号：US13336247

申请日：2011-12-23

申请人： Yumi HAYASHI ,  Akihiro KAJITA ,  Makoto WADA

发明人： Yumi HAYASHI ,  Akihiro KAJITA ,  Makoto WADA

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76877 ,  H01L21/76819 ,  H01L21/7682 ,  H01L21/76885 ,  H01L23/522 ,  H01L23/585 ,  H01L2224/32014

摘要： According to one embodiment, a semiconductor device includes a first insulating film formed on a substrate and including a first area and a second area; a groove formed in the first area of the first insulating film; a plurality of first wiring lines formed in the groove and on the first insulating film, and a second insulating film covering a top surface of the first insulating film and top surfaces of the first wiring lines, the plurality of first wiring lines are parallel to a sidewall of the groove and apart from each other with a first predetermined distance, and the first wiring line closest to the sidewall is apart from the sidewall with a second predetermined distance.

摘要翻译： 根据一个实施例，半导体器件包括形成在衬底上并包括第一区域和第二区域的第一绝缘膜; 形成在第一绝缘膜的第一区域中的槽; 形成在所述槽和所述第一绝缘膜上的多个第一布线，以及覆盖所述第一绝缘膜的顶面和所述第一布线的顶面的第二绝缘膜，所述多个第一布线平行于 并且第一预定距离彼此分开，并且最靠近侧壁的第一布线与第二预定距离的侧壁分开。

公开(公告)号：US20090289366A1

公开(公告)日：2009-11-26

申请号：US12463167

申请日：2009-05-08

申请人： Tadayoshi WATANABE ,  Yumi HAYASHI ,  Takamasa USUI

发明人： Tadayoshi WATANABE ,  Yumi HAYASHI ,  Takamasa USUI

IPC分类号： H01L23/52 ,  H01L21/768

CPC分类号： H01L21/7682 ,  H01L21/76807 ,  H01L21/76828 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76873 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one aspect of the present invention, a semiconductor device may include an inter-wiring dielectric film in which a wiring trench is formed, a metal wiring layer formed in the wiring trench in the inter-wiring dielectric film, a first barrier layer formed on a side surface of the wiring trench, the first barrier layer being an oxide film made from a metal different from a main constituent metal element in the wiring layer, a second barrier layer formed on a side surface of the wiring layer, the second barrier layer having a Si atom of the metal used in the wiring layer, and a gap formed between the first barrier layer and the second barrier layer.

摘要翻译： 在本发明的一个方面中，半导体器件可以包括布线​​电介质膜，其中形成布线沟槽，形成在布线电介质膜中的布线沟槽中的金属布线层，形成在布线电介质膜上的第一阻挡层 所述布线沟槽的侧表面，所述第一阻挡层是由与所述布线层中的主要构成金属元素不同的金属制成的氧化物膜，形成在所述布线层的侧表面上的第二阻挡层，所述第二阻挡层 具有在所述布线层中使用的金属的Si原子，以及在所述第一阻挡层和所述第二阻挡层之间形成的间隙。

公开(公告)号：US20130043604A1

公开(公告)日：2013-02-21

申请号：US13428569

申请日：2012-03-23

申请人： Yumi HAYASHI

发明人： Yumi HAYASHI

IPC分类号： H01L23/535 ,  H01L21/768

CPC分类号： H01L23/5283 ,  H01L21/764 ,  H01L21/76816 ,  H01L21/7682 ,  H01L21/76838 ,  H01L27/10855 ,  H01L27/10888 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11548 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to one embodiment, a semiconductor device includes a first insulating layer provided in a first area and in a second area, a line-and-space-like second insulating layer formed on the first insulating layer provided in the first area, and a third insulating layer formed on the first insulating layer provided in the second area and which is substantially identical to the second insulating layer in height.

摘要翻译： 根据一个实施例，半导体器件包括设置在第一区域和第二区域中的第一绝缘层，形成在设置在第一区域中的第一绝缘层上的线间隔状的第二绝缘层，以及第三绝缘层 绝缘层，形成在设置在第二区域中的与第二绝缘层基本相同的第一绝缘层上。

公开(公告)号：US20130119550A1

公开(公告)日：2013-05-16

申请号：US13570436

申请日：2012-08-09

申请人： Yumi HAYASHI

发明人： Yumi HAYASHI

IPC分类号： H01L23/48 ,  H01L21/28

CPC分类号： H01L27/0207 ,  H01L21/7682 ,  H01L21/76852 ,  H01L21/76885 ,  H01L23/535 ,  H01L2924/0002 ,  H01L2924/00

摘要： In one embodiment, a method of manufacturing a semiconductor device includes sequentially forming a first insulator, a second insulator, and a sacrificial layer on a semiconductor substrate, and forming plural core materials from the sacrificial layer and the second insulator. The method further includes forming first and second interconnects on side surfaces of each core material to form plural first interconnects and plural second interconnects alternately, each first interconnect having a first side surface in contact with a core material and a second side surface positioned on an opposite side of the first side surface, and each second interconnect having a third side surface in contact with a core material and a fourth side surface positioned on an opposite side of the third side surface. The method further includes removing the sacrificial layer so that the second insulator remains, after the first and second interconnects are formed.

摘要翻译： 在一个实施例中，制造半导体器件的方法包括在半导体衬底上顺序地形成第一绝缘体，第二绝缘体和牺牲层，以及从牺牲层和第二绝缘体形成多个芯材料。 该方法还包括在每个芯材的侧表面上形成第一和第二互连以交替形成多个第一互连和多个第二互连，每个第一互连具有与芯材接触的第一侧表面和位于相对的第二侧表面 并且每个第二互连具有与芯材接触的第三侧表面和位于所述第三侧表面的相对侧上的第四侧表面。 该方法还包括在形成第一和第二互连件之后去除牺牲层，使得第二绝缘体保留。

公开(公告)号：US20100207274A1

公开(公告)日：2010-08-19

申请号：US12708274

申请日：2010-02-18

申请人： Yumi HAYASHI ,  Hideki Shibata

发明人： Yumi HAYASHI ,  Hideki Shibata

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H01L21/76861 ,  H01L21/0273 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/32115 ,  H01L21/76814 ,  H01L21/76816 ,  H01L21/76826 ,  H01L21/76831 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device comprising a wiring suitable for miniaturization and manufacturing method thereof are disclosed. According to one aspect of the present invention, it is provided a semiconductor device comprising an insulator formed above a semiconductor substrate, and a wiring formed in the insulator and having surface roughness capable of suppressing surface scattering of electrons and reduction in electrical conductivity thereof.

摘要翻译： 公开了一种包括适于其小型化的布线的半导体器件及其制造方法。 根据本发明的一个方面，提供了一种半导体器件，其包括形成在半导体衬底上的绝缘体和形成在绝缘体中并具有能够抑制电子的表面散射和降低其导电性的表面粗糙度的布线。

公开(公告)号：US20100052028A1

公开(公告)日：2010-03-04

申请号：US12619229

申请日：2009-11-16

申请人： Yumi HAYASHI ,  Hayato Nasu ,  Kazumichi Tsumura ,  Takamasa Usui ,  Hiroyoshi Tanimoto

发明人： Yumi HAYASHI ,  Hayato Nasu ,  Kazumichi Tsumura ,  Takamasa Usui ,  Hiroyoshi Tanimoto

IPC分类号： H01L27/108

CPC分类号： H01L29/945 ,  H01L27/10852 ,  H01L27/1087 ,  H01L28/40 ,  H01L29/66181

摘要： A transistor formed on a semiconductor substrate has a gate electrode formed via a gate insulating film and first and second diffusion layers formed in the semiconductor substrate, the first and second diffusion layers being positioned at both sides of the gate electrode. A first electrode is connected to the first diffusion layer of the transistor. A capacitor insulating film formed on the first electrode is formed of a silicon oxide film containing a substrate which is faster than Cu in diffusion velocity and which more readily reacts with oxygen than Cu does. A second electrode formed on the capacitor insulating film is formed of one of a Cu layer and another Cu layer containing the substance.

摘要翻译： 形成在半导体衬底上的晶体管具有通过栅极绝缘膜形成的栅电极和形成在半导体衬底中的第一和第二扩散层，第一和第二扩散层位于栅电极的两侧。 第一电极连接到晶体管的第一扩散层。 形成在第一电极上的电容器绝缘膜由包含衬底的氧化硅膜形成，该衬底的扩散速度比Cu快，并且比Cu更容易与氧反应。 形成在电容器绝缘膜上的第二电极由Cu层和含有该物质的另一Cu层中的一个形成。