公开(公告)号：US3972756A

公开(公告)日：1976-08-03

申请号：US400924

申请日：1973-09-26

申请人： Akira Nagase ,  Masayasu Tsunematsu ,  Norio Anzai ,  Akihiro Tomozawa

发明人： Akira Nagase ,  Masayasu Tsunematsu ,  Norio Anzai ,  Akihiro Tomozawa

IPC分类号： H01L29/78 ,  H01L21/00 ,  H01L21/308 ,  H01L21/336 ,  H01L29/00 ,  H01L7/50

CPC分类号： H01L29/00 ,  H01L21/00 ,  H01L21/308 ,  H01L29/66477 ,  Y10S148/051 ,  Y10S148/053 ,  Y10S148/106

摘要： A method of producing an MIS structure having self-alignment construction, wherein an insulating film is formed on the surface of a semiconductor substrate, a semiconductor layer is formed on a selected area of the insulating film, parts of the insulating film are etched using the semiconductor layer as a mask, and the surface of the semiconductor layer is etched in such manner that the underlying insulating film may not be etched, whereby the marginal portion of the semiconductor layer which otherwise projects laterally beyond the underlying insulating film is caused to recede.

摘要翻译： 一种制造具有自对准结构的MIS结构的方法，其中在半导体衬底的表面上形成绝缘膜，在绝缘膜的选定区域上形成半导体层，使用 半导体层作为掩模，并且半导体层的表面被蚀刻，使得下面的绝缘膜可能不被蚀刻，由此导致横向延伸超过下面的绝缘膜的半导体层的边缘部分后退。

公开(公告)号：US4529456A

公开(公告)日：1985-07-16

申请号：US531708

申请日：1983-09-13

申请人： Norio Anzai ,  Hideki Yasuoka

发明人： Norio Anzai ,  Hideki Yasuoka

IPC分类号： H01L27/06 ,  H01L21/205 ,  H01L21/225 ,  H01L21/74 ,  H01L21/76 ,  H01L21/761 ,  H01L21/8249 ,  H01L21/265 ,  H01L21/20

CPC分类号： H01L21/225 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/74 ,  H01L21/761 ,  H01L21/8249 ,  H01L27/06

摘要： The present invention relates to a method of manufacturing a semiconductor integrated circuit device, especially a Bi-MOS IC. It comprises:1. introducing an impurity of a first conductivity type into a plurality of parts of one major surface of a substrate containing a first conductivity type impurity, to form a plurality of impurity-doped regions which have an impurity density higher than that of said substrate;2. forming an epitaxial semiconductor layer containing an impurity of a second conductivity type on the one major surface of said substrate;3. introducing a first conductivity type impurity simultaneously into those parts of a major surface of said epitaxial semiconductor layer which overlie said plurality of impurity doped regions; and4. introducing the first conductivity type impurity of said plurality of impurity-doped regions into said epitaxial semiconductor layer by drive-in diffusion, and subjecting to drive-in diffusion the first conductivity type impurity introduced in the major surface of said epitaxial semiconductor layer, to connect diffused layers formed by the respective diffusions and to form an isolation region and a semiconductor region for forming a MOS FET.MOS FETs can be formed in the semiconductor regions and bipolar transistors in a part of the epitaxial semiconductor layer.

摘要翻译： 本发明涉及制造半导体集成电路器件，特别是Bi-MOS IC的方法。 它包括：1.将含有第一导电类型的杂质引入到含有第一导电类型杂质的衬底的一个主表面的多个部分中，以形成杂质密度高于 所述基板; 2.在所述衬底的一个主表面上形成含有第二导电类型杂质的外延半导体层; 3.将第一导电类型杂质同时引入覆盖所述多个杂质掺杂区的所述外延半导体层的主表面的那些部分; 以及4.通过驱入扩散将所述多个杂质掺杂区的第一导电类型杂质引入所述外延半导体层，并且在所述外延半导体层的主表面中引入的第一导电类型杂质进行驱入扩散 连接由各个扩散部形成的扩散层，并形成用于形成MOS FET的隔离区域和半导体区域。 可以在外延半导体层的一部分中的半导体区域和双极晶体管中形成MOS FET。

公开(公告)号：US4662057A

公开(公告)日：1987-05-05

申请号：US759441

申请日：1985-07-26

申请人： Hideki Yasuoka ,  Yasunobu Tanizaki ,  Akira Muramatsu ,  Norio Anzai

发明人： Hideki Yasuoka ,  Yasunobu Tanizaki ,  Akira Muramatsu ,  Norio Anzai

IPC分类号： H01L29/78 ,  H01L21/76 ,  H01L21/8249 ,  H01L27/00 ,  H01L27/06 ,  H01L27/092 ,  H01L21/425

CPC分类号： H01L21/76 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/092

摘要： The present invention relates to a Bi-CMOS.IC, characterized by comprising a semiconductor substrate of a first conductivity type, and a semiconductor layer of a second conductivity type which is epitaxially grown on one major surface of said semiconductor substrate and which is electrically isolated into a plurality of semiconductor island regions by a thick surface oxide film formed by local oxidation and a semiconductor diffused layer of the first conductivity type formed between said oxide film and said substrate; a bipolar type semiconductor element being formed in one of said island regions, while CMOS type semiconductor elements are formed in the other island regions; the thick surface oxide film formed by the local oxidation being included between a base region and a collector contact region within said one island region formed with said bipolar type semiconductor element, while gate electrodes made of a semiconductor are disposed over said other island regions formed with said CMOS type semiconductor elements.

摘要翻译： 本发明涉及一种Bi-CMOS.IC，其特征在于包括第一导电类型的半导体衬底和第二导电类型的半导体层，其外延生长在所述半导体衬底的一个主表面上并且被电隔离 通过局部氧化形成的厚表面氧化膜和形成在所述氧化膜和所述衬底之间的第一导电类型的半导体扩散层而形成多个半导体岛区域; 在所述岛状区域之一上形成双极型半导体元件，在其他岛状区域形成有CMOS型半导体元件; 由局部氧化形成的厚表面氧化膜包括在形成有所述双极型半导体元件的所述一个岛状区域内的基极区域与集电极接触区域之间，而由半导体制成的栅极电极设置在形成有 所述CMOS型半导体元件。

公开(公告)号：US4258379A

公开(公告)日：1981-03-24

申请号：US78452

申请日：1979-09-24

申请人： Tomoyuki Watanabe ,  Takahiro Okabe ,  Minoru Nagata ,  Tohru Nakamura ,  Kenji Kaneko ,  Yutaka Okada ,  Norio Anzai ,  Takanori Nishimura ,  Takashi Agatsuma

发明人： Tomoyuki Watanabe ,  Takahiro Okabe ,  Minoru Nagata ,  Tohru Nakamura ,  Kenji Kaneko ,  Yutaka Okada ,  Norio Anzai ,  Takanori Nishimura ,  Takashi Agatsuma

IPC分类号： H01L21/74 ,  H01L21/761 ,  H01L21/8226 ,  H01L27/02 ,  H01L27/04 ,  H03K19/091

CPC分类号： H01L21/74 ,  H01L21/761 ,  H01L21/8226 ,  H01L27/0244

摘要： A semiconductor IC device in which an N-type semiconductor layer is formed in a P-type semiconductor substrate; the N-type layer is divided by a P.sup.+ -type insulation region into plural island regions; and an IIL is formed in a first island region while an NPN transistor is formed in a second island region, wherein an N-type up-diffused layer is formed from the bottom of the first island region up while an N-type well region is formed from the surface of the first island region down, and N.sup.+ -type buried layers are formed near the bottoms of the first and the second island region.

摘要翻译： 一种在P型半导体衬底中形成N型半导体层的半导体IC器件; N型层被P +型绝缘区划分成多个岛状区域; 并且在第一岛状区域中形成IIL，而在第二岛状区域中形成NPN晶体管，其中N型上扩散层从第一岛区的底部向上形成，而N型阱区为 从第一岛区域的表面向下形成，并且在第一岛区域和第二岛区域的底部附近形成N +型掩埋层。