公开(公告)号：US20110049221A1

公开(公告)日：2011-03-03

申请号：US12551960

申请日：2009-09-01

Applicant: Pascal P. Blais ,  Paul F. Fortier ,  Kang-Wook Lee ,  Jae-Woong Nah ,  Soojae Park ,  Robert L. Toutant ,  Alain A. Warren

Inventor： Pascal P. Blais ,  Paul F. Fortier ,  Kang-Wook Lee ,  Jae-Woong Nah ,  Soojae Park ,  Robert L. Toutant ,  Alain A. Warren

IPC: B23K37/04 ,  B23K31/00

CPC classification number: B23K1/0016 ,  H01L21/563 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/73204 ,  H01L2224/75704 ,  H01L2224/75985 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15787 ,  H01L2924/3511 ,  H01L2924/01026 ,  H01L2924/00

Abstract: A method and apparatus for making chip assemblies is disclosed that prevent or reduce the cracking and delamination of ultra low-k dielectrics in the back-end-of-line in Si chips that can occur during the chip assembly process. The method and apparatus apply pressure to the top and bottom surfaces of a substrate during the chip bonding process so that the bending and warping of the assembled modules are reduced. The reduced bending and warping prevent or reduce the cracking and delamination of ultra low-k dielectrics.

Abstract translation: 公开了一种用于制造芯片组件的方法和装置，其防止或减少在芯片组装过程中可能发生的Si芯片中后端的超低k电介质的开裂和分层。 该方法和装置在芯片接合过程期间对基板的顶表面和底表面施加压力，使得组装的模块的弯曲和翘曲减小。 减少弯曲和翘曲防止或减少超低k电介质的开裂和分层。

公开(公告)号：US09393633B2

公开(公告)日：2016-07-19

申请号：US12551960

申请日：2009-09-01

Applicant: Pascal P Blais ,  Paul F Fortier ,  Kang-Wook Lee ,  Jae-Woong Nah ,  Soojae Park ,  Robert L Toutant ,  Alain A Warren

Inventor： Pascal P Blais ,  Paul F Fortier ,  Kang-Wook Lee ,  Jae-Woong Nah ,  Soojae Park ,  Robert L Toutant ,  Alain A Warren

IPC: B23K20/00 ,  B23K1/00 ,  H01L21/56 ,  H01L23/00

CPC classification number: B23K1/0016 ,  H01L21/563 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/73204 ,  H01L2224/75704 ,  H01L2224/75985 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15787 ,  H01L2924/3511 ,  H01L2924/01026 ,  H01L2924/00

Abstract: A method and apparatus for making chip assemblies is disclosed that prevent or reduce the cracking and delamination of ultra low-k dielectrics in the back-end-of-line in Si chips that can occur during the chip assembly process. The method and apparatus apply pressure to the top and bottom surfaces of a substrate during the chip bonding process so that the bending and warping of the assembled modules are reduced. The reduced bending and warping prevent or reduce the cracking and delamination of ultra low-k dielectrics.

Abstract translation: 公开了一种用于制造芯片组件的方法和装置，其防止或减少在芯片组装过程中可能发生的Si芯片中后端的超低k电介质的开裂和分层。 该方法和装置在芯片接合过程期间对基板的顶表面和底表面施加压力，使得组装的模块的弯曲和翘曲减小。 减少弯曲和翘曲防止或减少超低k电介质的开裂和分层。

公开(公告)号：US20120292375A1

公开(公告)日：2012-11-22

申请号：US13566467

申请日：2012-08-03

Applicant: Pascal P. Blais ,  Paul F. Fortier ,  Kang-Wook Lee ,  Jae-Woong Nah ,  Soojae Park ,  Robert L. Toutant ,  Alain A. Warren

Inventor： Pascal P. Blais ,  Paul F. Fortier ,  Kang-Wook Lee ,  Jae-Woong Nah ,  Soojae Park ,  Robert L. Toutant ,  Alain A. Warren

IPC: B23K37/04

CPC classification number: B23K1/0016 ,  H01L21/563 ,  H01L24/75 ,  H01L24/81 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/73204 ,  H01L2224/75704 ,  H01L2224/75985 ,  H01L2224/81005 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01076 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15787 ,  H01L2924/3511 ,  H01L2924/01026 ,  H01L2924/00

Abstract: A method and apparatus for making chip assemblies is disclosed that prevent or reduce the cracking and delamination of ultra low-k dielectrics in the back-end-of-line in Si chips that can occur during the chip assembly process. The method and apparatus apply pressure to the top and bottom surfaces of a substrate during the chip bonding process so that the bending and warping of the assembled modules are reduced. The reduced bending and warping prevent or reduce the cracking and delamination of ultra low-k dielectrics.

Abstract translation: 公开了一种用于制造芯片组件的方法和装置，其防止或减少在芯片组装过程中可能发生的Si芯片中后端的超低k电介质的开裂和分层。 该方法和装置在芯片接合过程期间对基板的顶表面和底表面施加压力，使得组装的模块的弯曲和翘曲减小。 减小的弯曲和翘曲防止或减少超低k电介质的开裂和分层。