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公开(公告)号：US06560134B2
公开(公告)日：2003-05-06
申请号：US10014776
申请日：2001-11-07
IPC分类号： G11C502
CPC分类号： G11C5/025 , H01L23/50 , H01L24/02 , H01L27/10805 , H01L2924/01004 , H01L2924/01005 , H01L2924/01033 , H01L2924/01082
摘要： A memory configuration includes a central connection area. The central connection area is surrounded annularly by cell arrays having memory cells. The memory configuration has compact external dimensions and is suitable, in particular, for a side ratio of 2:1. All the peripheral circuits are preferably disposed in the central connection area. As a result, the propagation time differences between the peripheral circuits and the various cell arrays are relatively small.
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2.发明授权Loop-back method for measuring the interface timing of semiconductor devices with the aid of signatures and/or parity methods 有权借助于签名和/或奇偶校验方法测量半导体器件的接口时序的环回方法公开(公告)号：US07398444B2
公开(公告)日：2008-07-08
申请号：US11220332
申请日：2005-09-06
申请人： Martin Brox , Robert Kaiser , Volker Kilian , Wolfgang Spirkl
发明人： Martin Brox , Robert Kaiser , Volker Kilian , Wolfgang Spirkl
IPC分类号： G01R31/28
CPC分类号： G01R31/31725 , G01R31/31716 , G11C29/02 , G11C29/022 , G11C29/50 , G11C29/50012
摘要： The invention relates to a method for testing a memory device with the memory device being able to be operated in a normal operating mode and a test mode and encompassing an output driver, input driver, and data pads. The method includes the steps of communicating test input data to be used for a test to the memory device, performing a test using the test input data in order to obtain test output data, the test data read out being passed via an output driver, at least one data pad, and an input driver, wherein the input drivers and output drivers are switched during the test in such a way as to enable data to be simultaneously read from and written to the memory device, and creating a data test result from the test output data. Furthermore, the invention relates to a memory device and a system for testing a memory device.
摘要翻译： 本发明涉及一种用于测试存储器件的方法，该存储器件能够以正常操作模式和测试模式操作并且包含输出驱动器，输入驱动器和数据焊盘。 该方法包括以下步骤：将用于测试的测试输入数据传送到存储器件，使用测试输入数据执行测试，以便获得测试输出数据，读出的测试数据经由输出驱动器通过， 至少一个数据焊盘和输入驱动器，其中在测试期间切换输入驱动器和输出驱动器，使得能够同时从存储器件读取和写入数据，并且从 测试输出数据。 此外，本发明涉及用于测试存储器件的存储器件和系统。
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3.发明申请Loop-back method for measuring the interface timing of semiconductor devices with the aid of signatures and/or parity methods 有权借助于签名和/或奇偶校验方法测量半导体器件的接口时序的环回方法公开(公告)号：US20060059397A1
公开(公告)日：2006-03-16
申请号：US11220332
申请日：2005-09-06
申请人： Martin Brox , Robert Kaiser , Volker Kilian , Wolfgang Spirkl
发明人： Martin Brox , Robert Kaiser , Volker Kilian , Wolfgang Spirkl
CPC分类号： G01R31/31725 , G01R31/31716 , G11C29/02 , G11C29/022 , G11C29/50 , G11C29/50012
摘要： The invention relates to a method for testing a memory device with the memory device being able to be operated in a normal operating mode and a test mode and comprising output driver, input driver, and data pads. The method comprises the steps of communicating test input data to be used for a test to the memory device, performing a test using the test input data in order to obtain test output data, the test data read out being passed via an output driver, at least one data pad, and an input driver, wherein the input drivers and output drivers are switched during the test in such a way as to enable data to be simultaneously read from and written to the memory device, and creating a data test result from the test output data. Furthermore, the invention relates to a memory device and a system for testing a memory device.
摘要翻译： 本发明涉及一种用于测试存储器件的方法，该存储器件能够以正常操作模式和测试模式操作并且包括输出驱动器，输入驱动器和数据焊盘。 该方法包括以下步骤：将用于测试的测试输入数据传送到存储器件，使用测试输入数据执行测试，以便获得测试输出数据，读出的测试数据经由输出驱动器通过， 至少一个数据焊盘和输入驱动器，其中在测试期间切换输入驱动器和输出驱动器，使得能够同时从存储器件读取和写入数据，并且从 测试输出数据。 此外，本发明涉及用于测试存储器件的存储器件和系统。
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4.发明授权Configuration for generating signal impulses of defined lengths in a module with a bist-function 有权用于在具有双功能的模块中产生定义长度的信号脉冲的配置公开(公告)号：US06715118B2
公开(公告)日：2004-03-30
申请号：US09781208
申请日：2001-02-12
IPC分类号： G01R31317
CPC分类号： G01R31/31858 , H03K5/131 , H03K5/133
摘要： In the configuration, the module can “learn” one or more time intervals from the external tester and then repeat them internally or compare them to its own internally measured time intervals, for instance, for the purpose of evaluating whether the module in question has crossed a time specification value or remains below the value. The module can also measure and store one or more internal time intervals and transmit them to the external tester in digital or analog form.
摘要翻译： 在配置中，模块可以从外部测试器“学习”一个或多个时间间隔，然后在内部重复，或将其与其自身内部测量的时间间隔进行比较，例如，为了评估所讨论的模块是否已经越过 时间规格值或低于该值。 该模块还可以测量和存储一个或多个内部时间间隔，并以数字或模拟形式将其传输到外部测试仪。
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公开(公告)号：US06449206B2
公开(公告)日：2002-09-10
申请号：US09867292
申请日：2001-05-29
IPC分类号： G11C800
CPC分类号： G11C17/18
摘要： In order to program a programmable element, it is proposed in a semiconductor circuit configuration to connect a first and a second connecting terminal of a programmable element to first and/or second potential devices provided in the semiconductor circuit configuration. In this manner, the first and second potentials are intrinsically made available to form a burning voltage for programming the programmable element.
摘要翻译： 为了编程可编程元件，提出以半导体电路配置将可编程元件的第一和第二连接端子连接到设置在半导体电路配置中的第一和/或第二电位器件。 以这种方式，第一和第二电位本质上可用于形成用于编程可编程元件的燃烧电压。
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6.发明授权公开(公告)号：US06366518B1
公开(公告)日：2002-04-02
申请号：US09571486
申请日：2000-05-15
IPC分类号： G11C700
CPC分类号： G11C17/18
摘要： A circuit includes a programmable element having conductor track resistance that can be permanently altered by an electric current. The circuit also has a switchable element for receiving a control signal for programming the programmable element. The programmable element and the switchable element are connected in series between two supply potentials. The programmable element can have an electrical fuse. The input of a read-out circuit is connected through a protective circuit to the circuit node between the programmable element and the switchable element. The protective circuit serves for limiting the voltage potential at the input of the read-out circuit during a programming operation. The circuit elements of the read-out circuit can thus be dimensioned in an area-saving manner. The protective circuit also can include a diode having an anode connected to the input of the read-out circuit and a cathode connected to a third supply potential. The protective circuit can include resistors, one disposed between the anode and input of the read-out circuit and another disposed between the anode and the circuit node.
摘要翻译： 电路包括具有能够被电流永久改变的导体轨道电阻的可编程元件。 电路还具有用于接收用于编程可编程元件的控制信号的可切换元件。 可编程元件和可切换元件串联连接在两个电源之间。 可编程元件可以具有电熔丝。 读出电路的输入通过保护电路连接到可编程元件和可切换元件之间的电路节点。 保护电路用于在编程操作期间限制读出电路输入端的电压电位。 因此，读出电路的电路元件可以以面积节省的方式设计。 保护电路还可以包括具有连接到读出电路的输入端的阳极和连接到第三电源电位的阴极的二极管。 保护电路可以包括电阻器，一个设置在读出电路的阳极和输入端之间，另一个设置在阳极和电路节点之间。
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公开(公告)号：US06353357B1
公开(公告)日：2002-03-05
申请号：US09693769
申请日：2000-10-20
申请人： Robert Kaiser , Helmut Schneider
发明人： Robert Kaiser , Helmut Schneider
IPC分类号： G05F146
CPC分类号： H03K19/0027
摘要： An integrated circuit has a first control unit for controlling the threshold potential of the transistors of a first conductivity type. In addition, it has a second control unit for controlling the threshold potentials of the transistors of a second conductivity type. The required value input of the second control unit is supplied with a required value for the threshold potential of the transistors of the second conductivity type, which is proportional to the actual value of the threshold potential of the transistors of the first conductivity type. Due to the dependence of the second control unit on the control by the first control unit, improved switching characteristics of the integrated circuit are achieved.
摘要翻译： 集成电路具有用于控制第一导电类型的晶体管的阈值电位的第一控制单元。 此外，它具有用于控制第二导电类型的晶体管的阈值电位的第二控制单元。 第二控制单元的所需值输入被提供有与第一导电类型的晶体管的阈值电位的实际值成比例的第二导电类型的晶体管的阈值电位的所需值。 由于第二控制单元对第一控制单元的控制的依赖性，实现了集成电路的改进的开关特性。
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8.发明授权Integrated semiconductor memory configuration with self-buffering of supply voltages 有权具有电源电压自缓冲的集成半导体存储器配置公开(公告)号：US06236612B1
公开(公告)日：2001-05-22
申请号：US09523146
申请日：2000-02-22
IPC分类号： G11C700
CPC分类号： H01L27/108 , H01L23/5286 , H01L27/0214 , H01L27/105 , H01L2924/0002 , H01L2924/00
摘要： The integrated semiconductor memory configuration has a plurality of memory cell fields connected to one another by low-resistance supply lines forming a power network. The power network is connected to a voltage generator via a high-resistance supply line. An activated memory cell field is supplied, for the purpose of such activation, by self-buffering from the other memory cell fields (1-5, 7-8).
摘要翻译： 集成半导体存储器配置具有通过形成电力网络的低电阻供给线彼此连接的多个存储单元场。 电力网通过高电阻电源线连接到电压发生器。 激活的存储单元字段为了这种激活的目的，通过其他存储单元字段（1-5,7-8）的自缓冲来提供。
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公开(公告)号：US06178124B1
公开(公告)日：2001-01-23
申请号：US09401388
申请日：1999-09-22
IPC分类号： G11C700
CPC分类号： G11C29/835
摘要： The integrated memory has memory cells which are combined to form individually addressable standard units, and one or more redundant units for replacing one of the standard units on an address basis. The memory also has a self-test unit for performing a function test on the memory cells and for performing an analysis as to which of the standard units is to be replaced by a respective redundant unit. There is also a first memory unit for storing the address, determined by the self-test unit, of the standard unit which is to be replaced by the redundant unit, and a comparison unit connected to an address bus and to outputs of the first memory unit, for comparing an address present on the address bus with the address stored in the first memory unit. The comparison unit activates the redundant unit if a match is recognized. The first memory unit has at least one output which is connected to a corresponding output of the integrated circuit for outputting the respectively stored address.
摘要翻译： 集成存储器具有被组合以形成单独可寻址标准单元的存储单元，以及一个或多个冗余单元，用于以地址为基础替换标准单元之一。 存储器还具有用于对存储器单元执行功能测试并且用于执行关于哪个标准单元将被相应的冗余单元替换的分析的自检单元。 还存在用于存储由自检单元确定的由冗余单元替代的标准单元的地址的第一存储单元，以及连接到地址总线的比较单元和第一存储器的输出 单元，用于将地址总线上存在的地址与存储在第一存储器单元中的地址进行比较。 如果识别出匹配，比较单元激活冗余单元。 第一存储单元具有连接到集成电路的相应输出的至少一个输出，用于输出分别存储的地址。
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公开(公告)号：US06804166B2
公开(公告)日：2004-10-12
申请号：US10680773
申请日：2003-10-07
IPC分类号： G11C800
CPC分类号： G11C7/1012 , G11C7/1072 , G11C7/22
摘要： A data read access and a data write access is shared between two memory banks. A first memory bank of which is operated with a clock that is shifted by half a clock pulse with respect to the operating clock of the other, second memory bank. Partial data streams are combined at the output of the two memory banks to form a data stream with double the frequency.
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