公开(公告)号：US08404598B2

公开(公告)日：2013-03-26

申请号：US12851606

申请日：2010-08-06

申请人： Bryan Liao ,  Katsumasa Kawasaki ,  Yashaswini Pattar ,  Sergio Fukuda Shoji ,  Duy D. Nguyen ,  Kartik Ramaswamy ,  Ankur Agarwal ,  Phillip Stout ,  Shahid Rauf

发明人： Bryan Liao ,  Katsumasa Kawasaki ,  Yashaswini Pattar ,  Sergio Fukuda Shoji ,  Duy D. Nguyen ,  Kartik Ramaswamy ,  Ankur Agarwal ,  Phillip Stout ,  Shahid Rauf

IPC分类号： H01L21/302

CPC分类号： C23F1/00 ,  H01J37/32082 ,  H01J37/32146 ,  H01J37/32165 ,  H01L21/31116

摘要： Methods for processing a substrate are provided herein. In some embodiments, a method of etching a dielectric layer includes generating a plasma by pulsing a first RF source signal having a first duty cycle; applying a second RF bias signal having a second duty cycle to the plasma; applying a third RF bias signal having a third duty cycle to the plasma, wherein the first, second, and third signals are synchronized; adjusting a phase variance between the first RF source signal and at least one of the second or third RF bias signals to control at least one of plasma ion density non-uniformity in the plasma or charge build-up on the dielectric layer; and etching the dielectric layer with the plasma.

公开(公告)号：US20110031216A1

公开(公告)日：2011-02-10

申请号：US12851606

申请日：2010-08-06

申请人： BRYAN LIAO ,  KATSUMASA KAWASAKI ,  YASHASWINI PATTAR ,  SERGIO FUKUDA SHOJI ,  DUY D. NGUYEN ,  KARTIK RAMASWAMY ,  ANKUR AGARWAL ,  PHILLIP STOUT ,  SHAHID RAUF

发明人： BRYAN LIAO ,  KATSUMASA KAWASAKI ,  YASHASWINI PATTAR ,  SERGIO FUKUDA SHOJI ,  DUY D. NGUYEN ,  KARTIK RAMASWAMY ,  ANKUR AGARWAL ,  PHILLIP STOUT ,  SHAHID RAUF

IPC分类号： C23F1/00

CPC分类号： C23F1/00 ,  H01J37/32082 ,  H01J37/32146 ,  H01J37/32165 ,  H01L21/31116

摘要： Methods for processing a substrate are provided herein. In some embodiments, a method of etching a dielectric layer includes generating a plasma by pulsing a first RF source signal having a first duty cycle; applying a second RF bias signal having a second duty cycle to the plasma; applying a third RF bias signal having a third duty cycle to the plasma, wherein the first, second, and third signals are synchronized; adjusting a phase variance between the first RF source signal and at least one of the second or third RF bias signals to control at least one of plasma ion density non-uniformity in the plasma or charge build-up on the dielectric layer; and etching the dielectric layer with the plasma.

摘要翻译： 本文提供了处理基板的方法。 在一些实施例中，蚀刻介电层的方法包括通过脉冲具有第一占空比的第一RF源信号来产生等离子体; 向所述等离子体施加具有第二占空比的第二RF偏置信号; 向所述等离子体施加具有第三占空比的第三RF偏置信号，其中所述第一，第二和第三信号被同步; 调整所述第一RF源信号和所述第二或第三RF偏置信号中的至少一个之间的相位差，以控制所述等离子体中的等离子体或电荷积聚中的等离子体离子密度不均匀性中的至少一个; 并用等离子体蚀刻电介质层。

公开(公告)号：US20070196988A1

公开(公告)日：2007-08-23

申请号：US11360796

申请日：2006-02-23

申请人： Mehul Shroff ,  Mark Hall ,  Paul Grudowski ,  Tab Stephens ,  Phillip Stout ,  Olubunmi Adetutu

发明人： Mehul Shroff ,  Mark Hall ,  Paul Grudowski ,  Tab Stephens ,  Phillip Stout ,  Olubunmi Adetutu

IPC分类号： H01L21/336

CPC分类号： H01L21/28035 ,  H01L21/28123 ,  H01L21/32155 ,  H01L21/823437 ,  H01L21/823828

摘要： A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack (32) formed over a substrate (11), thereby forming an etched gate (92, 94) having a vertical sidewall profile by implanting the gate stack (32) with a nitrogen (42) and a dopant (52) and then heating the polysilicon gate stack (32) at a selected temperature using rapid thermal annealing (62) to anneal the nitrogen and dopant so that subsequent etching of the polysilicon gate stack (32) creates an etched gate (92, 94) having more idealized vertical gate sidewall profiles.

摘要翻译： 半导体工艺和设备使用预定的图案化和蚀刻步骤序列来蚀刻在衬底（11）上形成的栅极堆叠（32），从而通过注入栅叠层而形成具有垂直侧壁轮廓的蚀刻栅极（92,94） （32）和氮（42）和掺杂剂（52），然后使用快速热退火（62）在选定的温度下加热多晶硅栅极堆叠（32）以退火氮和掺杂剂，从而随后蚀刻多晶硅栅极 堆叠（32）产生具有更理想化的垂直栅极侧壁轮廓的蚀刻栅极（92,94）。