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128 条记录 (耗时 0.026 秒)

    Poly pre-doping anneals for improved gate profiles
    1.
    发明申请
    Poly pre-doping anneals for improved gate profiles 审中-公开
    聚预掺杂退火以改善浇口型材

    公开(公告)号：US20070196988A1

    公开(公告)日：2007-08-23

    申请号：US11360796

    申请日：2006-02-23

    申请人： Mehul Shroff ,  Mark Hall ,  Paul Grudowski ,  Tab Stephens ,  Phillip Stout ,  Olubunmi Adetutu

    发明人： Mehul Shroff ,  Mark Hall ,  Paul Grudowski ,  Tab Stephens ,  Phillip Stout ,  Olubunmi Adetutu

    IPC分类号： H01L21/336

    CPC分类号： H01L21/28035 ,  H01L21/28123 ,  H01L21/32155 ,  H01L21/823437 ,  H01L21/823828

    摘要： A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack (32) formed over a substrate (11), thereby forming an etched gate (92, 94) having a vertical sidewall profile by implanting the gate stack (32) with a nitrogen (42) and a dopant (52) and then heating the polysilicon gate stack (32) at a selected temperature using rapid thermal annealing (62) to anneal the nitrogen and dopant so that subsequent etching of the polysilicon gate stack (32) creates an etched gate (92, 94) having more idealized vertical gate sidewall profiles.

    摘要翻译： 半导体工艺和设备使用预定的图案化和蚀刻步骤序列来蚀刻在衬底（11）上形成的栅极堆叠（32），从而通过注入栅叠层而形成具有垂直侧壁轮廓的蚀刻栅极（92,94） （32）和氮（42）和掺杂剂（52），然后使用快速热退火（62）在选定的温度下加热多晶硅栅极堆叠（32）以退火氮和掺杂剂，从而随后蚀刻多晶硅栅极 堆叠（32）产生具有更理想化的垂直栅极侧壁轮廓的蚀刻栅极（92,94）。

    Undoped gate poly integration for improved gate patterning and cobalt silicide extendibility
    2.
    发明申请
    Undoped gate poly integration for improved gate patterning and cobalt silicide extendibility 失效
    未掺杂的栅极聚合，用于改进栅极图案化和硅化钴可扩展性

    公开(公告)号：US20070218661A1

    公开(公告)日：2007-09-20

    申请号：US11375768

    申请日：2006-03-15

    申请人： Mehul Shroff ,  Paul Grudowski ,  Mark Hall ,  Tab Stephens

    发明人： Mehul Shroff ,  Paul Grudowski ,  Mark Hall ,  Tab Stephens

    IPC分类号： H01L21/04

    CPC分类号： H01L21/82345 ,  H01L21/823418 ,  H01L21/823456 ,  H01L21/823462

    摘要： A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch an intrinsic polysilicon layer (26) formed over a substrate (11), thereby forming etched gates (62, 64) having vertical sidewall profiles (61, 63). While a blanket nitrogen implant (46) of the intrinsic polysilicon layer (26) may occur prior to gate etch, more idealized vertical gate sidewall profiles (61, 63) are obtained by fully doping the gates (80, 100) during the source/drain implantation steps (71, 77, 91, 97) and after the gate etch.

    摘要翻译： 半导体工艺和设备使用预定的图案化和蚀刻步骤序列来蚀刻在衬底（11）上形成的本征多晶硅层（26），从而形成具有垂直侧壁轮廓（61,63）的蚀刻栅极（62,64）。 虽然本征多晶硅层（26）的覆盖氮氮注入（46）可以在栅极蚀刻之前发生，但是在源极/漏极中通过完全掺杂栅极（80,100）来获得更理想化的垂直栅极侧壁轮廓（61,63） 漏极注入步骤（71,77,91,97）和栅极蚀刻之后。

    Plasma treatment for surface of semiconductor device
    3.
    发明申请
    Plasma treatment for surface of semiconductor device 失效
    半导体器件表面等离子体处理

    公开(公告)号：US20060105568A1

    公开(公告)日：2006-05-18

    申请号：US10987790

    申请日：2004-11-12

    申请人： Jin Shen ,  Brian Fisher ,  Mark Hall ,  Kurt Junker ,  Vikas Sheth ,  Mehul Shroff

    发明人： Jin Shen ,  Brian Fisher ,  Mark Hall ,  Kurt Junker ,  Vikas Sheth ,  Mehul Shroff

    IPC分类号： H01L21/44

    CPC分类号： H01L21/32139 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/0276 ,  H01L21/3105 ,  H01L21/31612

    摘要： A method for forming a semiconductor device (10) includes forming an organic anti-reflective coating (OARC) layer (18) over the semiconductor device (10). A tetra-ethyl-ortho-silicate (TEOS) layer (20) is formed over the OARC layer (18). The TEOS layer (20) is exposed to oxygen-based plasma at a temperature of at most about 300 degrees Celsius. In an alternative embodiment, the TEOS layer (20) is first exposed to a nitrogen-based plasma before being exposed to the oxygen-based plasma. A photoresist layer (22) is formed over the TEOS layer (20) and patterned. By applying oxygen based plasma and nitrogen based plasma to the TEOS layer (20) before applying photoresist, pattern defects are reduced.

    摘要翻译： 一种用于形成半导体器件（10）的方法包括在半导体器件（10）上形成有机抗反射涂层（OARC）层（18）。 在OARC层（18）上形成四乙基原硅酸盐（TEOS）层（20）。 TEOS层（20）在至多约300摄氏度的温度下暴露于基于氧的等离子体。 在替代实施例中，首先将TEOS层（20）暴露于基于氧的等离子体之前的氮基等离子体。 光致抗蚀剂层（22）形成在TEOS层（20）上并被图案化。 在施加光致抗蚀剂之前，通过将氧基等离子体和氮基等离子体施加到TEOS层（20）上，减少了图案缺陷。

    EPI T-gate structure for CoSi2 extendibility
    5.
    发明申请
    EPI T-gate structure for CoSi2 extendibility 有权
    EPI T-gate结构，CoSi2可扩展性

    公开(公告)号：US20070173004A1

    公开(公告)日：2007-07-26

    申请号：US11340049

    申请日：2006-01-26

    申请人： Mark Hall ,  Dharmesh Jawarani ,  Mehul Shroff ,  Edward Travis

    发明人： Mark Hall ,  Dharmesh Jawarani ,  Mehul Shroff ,  Edward Travis

    IPC分类号： H01L21/8234 ,  H01L21/336

    CPC分类号： H01L21/28114 ,  H01L29/42376 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    摘要： A semiconductor process and apparatus provide a T-shaped structure (96) formed from a polysilicon structure (10) and an epitaxially grown polysilicon layer (70) and having a narrower bottom critical dimension (e.g., at or below 40 nm) and a larger top critical dimension (e.g., at or above 40 nm) so that a silicide may be formed from a first material (such as CoSi2) in at least the upper region (90) of the T-shaped structure (96) without incurring the increased resistance caused by agglomeration and voiding that can occur with certain silicides at the smaller critical dimensions.

    摘要翻译： 半导体工艺和装置提供由多晶硅结构（10）和外延生长的多晶硅层（70）形成并且具有较窄的底部临界尺寸（例如，等于或低于40nm）形成的T形结构（96）和更大的 顶部临界尺寸（例如，40nm以上），使得硅化物可以至少在T形的上部区域（90）中由第一材料（例如CoSi 2 N 2）形成 结构（96），而不会导致由于在较小临界尺寸下某些硅化物可能发生的团聚和排空引起的增加的电阻。

    Spacer T-gate structure for CoSi2 extendibility
    6.
    发明申请
    Spacer T-gate structure for CoSi2 extendibility 有权
    CoSi2可扩展性的间隔T门结构

    公开(公告)号：US20070173002A1

    公开(公告)日：2007-07-26

    申请号：US11339953

    申请日：2006-01-26

    申请人： Mark Hall ,  Dharmesh Jawarani ,  Mehul Shroff ,  Edward Travis

    发明人： Mark Hall ,  Dharmesh Jawarani ,  Mehul Shroff ,  Edward Travis

    IPC分类号： H01L21/338 ,  H01L21/4763

    CPC分类号： H01L29/6656 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

    摘要： A semiconductor process and apparatus provide a T-shaped structure (84) formed from a polysilicon structure (10) and polysilicon spacers (80, 82) and having a narrower bottom dimension (e.g., at or below 40 nm) and a larger top critical dimension (e.g., at or above 40 nm) so that a silicide may be formed from a first material (such as CoSi2) in at least the upper region (100) of the T-shaped structure (84) without incurring the increased resistance caused by agglomeration and voiding that can occur with certain silicides at the smaller critical dimensions.

    摘要翻译： 半导体工艺和设备提供由多晶硅结构（10）和多晶硅间隔物（80,82）形成并且具有较窄的底部尺寸（例如，等于或低于40nm）的T形结构（84）和较大的顶部关键 尺寸（例如，在40nm以上），使得硅化物可以在至少T形结构的上部区域（100）中由第一材料（例如CoSi 2 N 2）形成（ 84），而不会导致由于在较小临界尺寸下某些硅化物可能发生的附聚和空隙引起的增加的电阻。

    Apparatus for distributing short-range wireless signals using an interconnection protocol for electronic devices
    10.
    发明授权
    Apparatus for distributing short-range wireless signals using an interconnection protocol for electronic devices 有权

    公开(公告)号：US10681761B2

    公开(公告)日：2020-06-09

    申请号：US15601413

    申请日：2017-05-22

    申请人： David R. Hall ,  Mark Hall ,  John Robinson ,  Joe Fox

    发明人： David R. Hall ,  Mark Hall ,  John Robinson ,  Joe Fox

    IPC分类号： H01Q1/00 ,  H04W76/15 ,  H04B7/04 ,  H04L29/08 ,  H04W56/00 ,  H04W4/80 ,  H04W76/11

    摘要： An apparatus for distributing data using a short-range wireless interconnection protocol for electronic devices includes a processor communicatively connected, using a communication bus, to a number of originator antennas, each of the number of originator antennas communicating with an originating device, a plurality of device antennas, communicatively connected to the communication bus, each of the plurality of device antennas communicating with a number of client devices, and a non-transitory storage medium. The non-transitory storage medium includes a receive module, a session identify module, and a send module. The receive module receives a data packet using one of the number of originator antennas. The session identify module identifies at least one communication session with at least one remote device associated with one of the plurality of device antennas. The send module sends the data packet to the at least one remote device associated with one of the plurality of device antennas.