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    METHOD FOR STACKING ELECTRONIC COMPONENTS
    1.
    发明申请
    METHOD FOR STACKING ELECTRONIC COMPONENTS 有权
    堆叠电子元件的方法

    公开(公告)号：US20130343027A1

    公开(公告)日：2013-12-26

    申请号：US13533576

    申请日：2012-06-26

    申请人： Maurice Perea ,  Allen Hill ,  Reggie Phillips

    发明人： Maurice Perea ,  Allen Hill ,  Reggie Phillips

    IPC分类号： H05K7/04 ,  H01G9/00

    CPC分类号： H01G4/30 ,  H01C1/014 ,  H01C1/14 ,  H01G4/232 ,  Y10T29/417 ,  Y10T29/43

    摘要： A method of forming a stacked electronic component, and an electronic component formed by the method wherein the method includes: providing a multiplicity of electronic components wherein each electronic component comprises a first external termination and a second external termination; providing a first lead frame plate and a second lead frame plate wherein the first lead frame plate and the second lead frame plate comprises barbs and leads; providing a molded case comprising a cavity and a bottom; and forming a sandwich of electronic components in an array between the first lead frame plate and the second lead frame plate with the barbs protruding towards the electronic components and the leads extending through the bottom.

    摘要翻译： 一种形成层叠电子元件的方法，以及通过该方法形成的电子部件，其中该方法包括：提供多个电子部件，其中每个电子部件包括第一外部端接和第二外部端接; 提供第一引线框架板和第二引线框架板，其中第一引线框架板和第二引线框架板包括倒钩和引线; 提供包括空腔和底部的模制外壳; 以及在所述第一引线框架板和所述第二引线框架板之间以阵列形式形成电子部件的夹层，所述倒钩朝向所述电子部件突出并且所述引线延伸穿过所述底部。

    Method for stacking electronic components
    4.
    发明授权
    Method for stacking electronic components 有权
    电子元器件堆放方法

    公开(公告)号：US08873219B2

    公开(公告)日：2014-10-28

    申请号：US13533576

    申请日：2012-06-26

    申请人： Maurice Perea ,  Allen Hill ,  Reggie Phillips

    发明人： Maurice Perea ,  Allen Hill ,  Reggie Phillips

    IPC分类号： H01G4/005 ,  H01G4/38

    CPC分类号： H01G4/30 ,  H01C1/014 ,  H01C1/14 ,  H01G4/232 ,  Y10T29/417 ,  Y10T29/43

    摘要： A method of forming a stacked electronic component, and an electronic component formed by the method wherein the method includes: providing a multiplicity of electronic components wherein each electronic component comprises a first external termination and a second external termination; providing a first lead frame plate and a second lead frame plate wherein the first lead frame plate and the second lead frame plate comprises barbs and leads; providing a molded case comprising a cavity and a bottom; and forming a sandwich of electronic components in an array between the first lead frame plate and the second lead frame plate with the barbs protruding towards the electronic components and the leads extending through the bottom.

    摘要翻译： 一种形成层叠电子元件的方法，以及通过该方法形成的电子部件，其中该方法包括：提供多个电子部件，其中每个电子部件包括第一外部端接和第二外部端接; 提供第一引线框架板和第二引线框架板，其中第一引线框架板和第二引线框架板包括倒钩和引线; 提供包括空腔和底部的模制外壳; 以及在所述第一引线框架板和所述第二引线框架板之间以阵列形式形成电子部件的夹层，所述倒钩朝向所述电子部件突出并且所述引线延伸穿过所述底部。

    MULTILAYERED CERAMIC CAPACITOR WITH IMPROVED LEAD FRAME ATTACHMENT
    5.
    发明申请
    MULTILAYERED CERAMIC CAPACITOR WITH IMPROVED LEAD FRAME ATTACHMENT 审中-公开
    多层陶瓷电容器与改进的引线框架连接

    公开(公告)号：US20130107419A1

    公开(公告)日：2013-05-02

    申请号：US13283784

    申请日：2011-10-28

    申请人： R. Allen Hill ,  Philip M. Lessner ,  Reggie Phillips ,  Keith Brown ,  James B. Byrd

    发明人： R. Allen Hill ,  Philip M. Lessner ,  Reggie Phillips ,  Keith Brown ,  James B. Byrd

    IPC分类号： H01G4/008 ,  H01G7/00

    CPC分类号： H01G2/06 ,  H01G4/008 ,  H01G4/232 ,  H01G4/2325 ,  H01G4/30 ,  Y10T29/43

    摘要： A capacitor with improved lead frame attachment is described wherein the improved lead frame attachment mitigates defects. The capacitor comprises parallel conductive internal electrodes of alternating polarity with a dielectric between the conductive internal electrodes. A first copper undercoat is in electrical contact with the conductive internal electrodes of a first polarity and a second copper undercoat is in electrical contact with conductive internal electrodes of a second polarity. A first lead is in electrical contact with the first copper undercoat with a first solder between the first lead and the first copper undercoat. A second lead is in electrical contact with the second copper undercoat with a second solder between the second lead and the second copper undercoat.

    摘要翻译： 描述了具有改进的引线框架附件的电容器，其中改进的引线框架附件减轻了缺陷。 电容器包括具有交替极性的平行导电内部电极与导电内部电极之间的电介质。 第一铜底涂层与第一极性的导电内部电极电接触，并且第二铜底涂层与第二极性的导电内部电极电接触。 第一引线与第一铜底涂层电接触，在第一引线和第一铜底涂层之间具有第一焊料。 第二引线与第二铜底涂层电接触，在第二引线和第二铜底涂层之间具有第二焊料。

    Leaded multi-layer ceramic capacitor with low ESL and low ESR
    6.
    发明授权
    Leaded multi-layer ceramic capacitor with low ESL and low ESR 有权
    具有低ESL和低ESR的带铅多层陶瓷电容器

    公开(公告)号：US08331078B2

    公开(公告)日：2012-12-11

    申请号：US12732549

    申请日：2010-03-26

    申请人： John E. McConnell ,  Reggie Phillips ,  Alan P. Webster ,  John Bultitude ,  Mark R. Laps ,  Lonnie G. Jones ,  Garry Renner

    发明人： John E. McConnell ,  Reggie Phillips ,  Alan P. Webster ,  John Bultitude ,  Mark R. Laps ,  Lonnie G. Jones ,  Garry Renner

    IPC分类号： H01G4/228

    CPC分类号： H01G4/30 ,  H01G2/065 ,  H01G4/232 ,  H05K3/3426

    摘要： A multi-layered ceramic capacitor with at least one chip and with first base metal plates in a parallel spaced apart relationship and second base metal plates in a parallel spaced apart relationship wherein the first plates and second plates are interleaved. A dielectric is between the first base metal plates and said second base metal plates and the dielectric has a first coefficient of thermal expansion. A first termination is in electrical contact with the first plates and a second termination is in electrical contact with the second plates. Lead frames are attached to, and in electrical contact with, the terminations wherein the lead frames have a second coefficient of thermal expansion and the second coefficient of thermal expansion is higher than said first coefficient of thermal expansion. The lead frame is a non-ferrous material.

    摘要翻译： 一种多层陶瓷电容器，其具有至少一个芯片，并且具有平行隔开的关系的第一基底金属板和平行隔开的关系的第二基底金属板，其中第一板和第二板被交错。 电介质位于第一基底金属板和第二基底金属板之间，电介质具有第一热膨胀系数。 第一端接件与第一板电接触，第二端接件与第二板电接触。 引线框架连接到端子处并与其接触，其中引线框架具有第二热膨胀系数，并且第二热膨胀系数高于所述第一热膨胀系数。 引线框架是有色金属材料。

    LEADED MULTI-LAYER CERAMIC CAPACITOR WITH LOW ESL AND LOW ESR
    7.
    发明申请
    LEADED MULTI-LAYER CERAMIC CAPACITOR WITH LOW ESL AND LOW ESR 有权
    领先的多层陶瓷电容器，具有低ESL和低ESR

    公开(公告)号：US20100243307A1

    公开(公告)日：2010-09-30

    申请号：US12732549

    申请日：2010-03-26

    申请人： John E. McConnell ,  Reggie Phillips ,  Alan P. Webster ,  John Bultitude ,  Mark R. Laps ,  Lonnie G. Jones ,  Garry Renner

    发明人： John E. McConnell ,  Reggie Phillips ,  Alan P. Webster ,  John Bultitude ,  Mark R. Laps ,  Lonnie G. Jones ,  Garry Renner

    IPC分类号： H01G4/228 ,  H05K1/18

    CPC分类号： H01G4/30 ,  H01G2/065 ,  H01G4/232 ,  H05K3/3426

    摘要： A multi-layered ceramic capacitor with at least one chip and with first base metal plates in a parallel spaced apart relationship and second base metal plates in a parallel spaced apart relationship wherein the first plates and second plates are interleaved. A dielectric is between the first base metal plates and said second base metal plates and the dielectric has a first coefficient of thermal expansion. A first termination is in electrical contact with the first plates and a second termination is in electrical contact with the second plates. Lead frames are attached to, and in electrical contact with, the terminations wherein the lead frames have a second coefficient of thermal expansion and the second coefficient of thermal expansion is higher than said first coefficient of thermal expansion. The lead frame is a non-ferrous material.

    摘要翻译： 一种多层陶瓷电容器，其具有至少一个芯片，并且具有平行隔开的关系的第一基底金属板和平行隔开的关系的第二基底金属板，其中第一板和第二板被交错。 电介质位于第一基底金属板和第二基底金属板之间，电介质具有第一热膨胀系数。 第一端接件与第一板电接触，第二端接件与第二板电接触。 引线框架连接到端子处并与其接触，其中引线框架具有第二热膨胀系数，并且第二热膨胀系数高于所述第一热膨胀系数。 引线框架是有色金属材料。