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27 条记录 (耗时 0.024 秒)

    Laminated diamond substrate
    1.
    发明授权
    Laminated diamond substrate 失效
    层压金刚石基材

    公开(公告)号：US5441791A

    公开(公告)日：1995-08-15

    申请号：US66753

    申请日：1993-05-24

    申请人： Richard C. Eden

    发明人： Richard C. Eden

    IPC分类号： B32B15/04 ,  C01B31/06 ,  C30B29/04 ,  F28F3/00 ,  H01L21/48 ,  H01L23/15 ,  H01L23/373 ,  H05K1/03 ,  H01L21/58

    CPC分类号： H01L21/4803 ,  H01L23/3732 ,  H01L2924/0002 ,  Y10T428/24355 ,  Y10T428/24364 ,  Y10T428/24479 ,  Y10T428/24521 ,  Y10T428/24529 ,  Y10T428/24975 ,  Y10T428/25 ,  Y10T428/2991 ,  Y10T428/2998 ,  Y10T428/30 ,  Y10T428/31504

    摘要： A synthetic diamond wafer grown by deposition from a plasma has a smooth, substrate side face and a rough, deposition side face. The rough face is coated with a bonding agent which fills the valleys and is finished so that its surface is parallel to the substrate side face to permit photolithographic processing of the wafer. Also disclosed is a multi-wafer laminate of two or more diamond film layers bonded together with an interlayer. Smooth, flat outer faces of the layers are oriented mutually parallel. The inner, bonded faces may be rough. A filler of diamond particles in the bonding agent improves the thermal conductivity of the laminate.

    摘要翻译： 通过从等离子体沉积而生长的合成金刚石晶片具有光滑的基板侧面和粗糙的沉积侧面。 粗糙的表面涂覆有填充谷的粘合剂并且被完成，使得其表面平行于基底侧面以允许晶片的光刻处理。 还公开了两个或更多个与中间层结合在一起的金刚石膜层的多晶片层压体。 层的平滑，平坦的外表面相互平行取向。 内部粘合面可能很粗糙。 粘合剂中金刚石颗粒的填料提高了层压板的导热性。

    Narrow-band inverted homo-heterojunction avalanche photodiode
    3.
    发明授权
    Narrow-band inverted homo-heterojunction avalanche photodiode 失效
    窄带反相同异质结雪崩光电二极管

    公开(公告)号：US4110778A

    公开(公告)日：1978-08-29

    申请号：US808496

    申请日：1977-06-21

    申请人： Richard C. Eden ,  Kenichi Nakano

    发明人： Richard C. Eden ,  Kenichi Nakano

    IPC分类号： H01L31/107 ,  H01L27/14

    CPC分类号： H01L31/107

    摘要： A narrow-band, inverted homo-heterojunction avalanche photodiode, configured in the shape of a mesa situated upon a substrate which is transparent to selected light energy wavelengths. The diode is inverted for operation such that the incoming light energy enters the substrate side, passes through a wavelength selective buffer layer and is absorbed upon entering the succeeding, active region. Avalanche gain is attained by drift from the area of absorption to the high field p-n homo-heterojunction located immediately thereafter. The device exhibits low levels of noise during operation because absorption is occurring in a low field region and because the ionization and breakdown noise associated with lattice mismatches is avoided through the formation of the p-n homo-heterojunction in one continuous growth process. Appropriate passivation of the mesa walls inhibits surface leakage and breakdown effects.

    摘要翻译： 窄带，反相同异质结雪崩光电二极管，其被配置为位于对选择的光能波长透明的衬底上的台面形状。 二极管被反相操作，使得入射光能进入衬底侧，通过波长选择缓冲层，并在进入后续有源区时被吸收。 通过从吸收区域漂移到紧邻的高场p-n同异质结获得雪崩增益。 该装置在操作期间表现出低水平的噪声，因为在低场区域中发生吸收，并且由于通过在一个连续生长过程中形成p-n同异质结来避免与晶格失配相关的电离和击穿噪声。 台面壁的适当钝化可以抑制表面渗漏和击穿效应。

    Sensitive high speed solid state preamp
    4.
    发明授权
    Sensitive high speed solid state preamp 失效
    敏感高速固体状态预处理

    公开(公告)号：US4075576A

    公开(公告)日：1978-02-21

    申请号：US772173

    申请日：1977-02-25

    申请人： Richard C. Eden

    发明人： Richard C. Eden

    IPC分类号： H03F3/08 ,  H04B10/158 ,  H03F3/16

    CPC分类号： H04B10/693 ,  H03F3/08

    摘要： A preamp for coupling to an avalanche photodiode (APD) of an optical receiver has an input stage including a dual gate field effect transistor (FET) and a single gate FET coupled in a cascade arrangement. The dual gate FET has its first gate coupled to the output of the APD, its second gate and source grounded, and its drain driving the gate of the single gate FET in a cascade arrangement. The source of the single gate FET is level-shifted and coupled by means of a feedback resistor to the first gate of the dual gate FET to provide a negative feedback. The output stage is a third FET with its gate coupled through a blocking capacitor to the source of the single gate FET in the input stage and with its drain providing the output of the preamp. In a preferred embodiment, the FETs used are GaAs FETs (GAASFETs).

    Method and device for precise geolocation of low-power, broadband, amplitude-modulated signals
    5.
    发明授权
    Method and device for precise geolocation of low-power, broadband, amplitude-modulated signals 失效
    低功耗，宽带，幅度调制信号精确定位的方法和装置

    公开(公告)号：US06759983B2

    公开(公告)日：2004-07-06

    申请号：US10107811

    申请日：2002-03-28

    申请人： Richard C. Eden

    发明人： Richard C. Eden

    IPC分类号： G01S302

    CPC分类号： G01S5/04 ,  G01S3/36 ,  G01S7/021

    摘要： The invention relates to methods and devices for precise geolocation of low-power, broadband, amplitude-modulated rf and microwave signals having poor coherency. The invention provides a basis for dramatic improvements in RF receiver technology, offering much higher sensitivity, very strong rejection of unintended signals, and novel direction finding techniques. When mounted on an airborne surveillance platform, the invention can detect and geolocate weak, broadband, incoherent RF and/or microwave signals. Embodiments of the invention are implemented by dual channel receivers (heterodyne or tuned-RF) that use crystal detection and Fast Fourier Transform (FFT) analysis for geolocation. Geolocation is accomplished using a subsystem of phased arrays and an angle of arrival technique.

    摘要翻译： 本发明涉及具有差相干性的低功率，宽带，幅度调制rf和微波信号的精确地理定位的方法和装置。 本发明为RF接收机技术的显着改进提供了基础，提供了更高的灵敏度，非常强的拒绝非预期信号以及新颖的方向发现技术。 当安装在机载监视平台上时，本发明可以检测和定位弱，宽带，非相干RF和/或微波信号。 本发明的实施例由对待地理定位使用晶体检测和快速傅立叶变换（FFT）分析的双通道接收器（外差或调谐RF）来实现。 使用相控阵列子系统和到达角技术实现地理定位。

    High temperature superconducting tunable filter with an adjustable capacitance gap
    6.
    发明授权
    High temperature superconducting tunable filter with an adjustable capacitance gap 有权
    高温超导可调滤波器，可调电容间隙

    公开(公告)号：US06662029B2

    公开(公告)日：2003-12-09

    申请号：US10023575

    申请日：2001-12-17

    申请人： Richard C. Eden ,  Balam A. Willemsen ,  George L. Matthaei

    发明人： Richard C. Eden ,  Balam A. Willemsen ,  George L. Matthaei

    IPC分类号： H03H701

    CPC分类号： H01P7/088 ,  H01G5/16 ,  H01G5/40 ,  H01P7/082 ,  H03J2200/10 ,  Y10S505/70 ,  Y10S505/705 ,  Y10S505/866

    摘要： A tunable filter having a fixed substrate, a first and second plate comprising a high-temperature superconductor material on the fixed substrate, a movable substrate, a mechanical driver attached to the fixed substrate and the movable substrate, a floating plate comprising a high-temperature superconductor material on the fixed substrate wherein the floating plate, the first plate, and the second plate define a gap, and wherein the gap is varied by length changes in the mechanical driver is provided.

    摘要翻译： 一种具有固定基板的可调滤光器，在固定基板上包括高温超导体材料的第一和第二板，可移动基板，附着到固定基板和可移动基板的机械驱动器，包括高温 在所述固定基板上的超导体材料，其中所述浮动板，所述第一板和所述第二板限定间隙，并且其中所述间隙由所述机械驱动器中的长度变化而变化。

    Low power, high speed random access memory circuit
    7.
    发明授权
    Low power, high speed random access memory circuit 失效
    低功耗，高速随机存取电路

    公开(公告)号：US4575821A

    公开(公告)日：1986-03-11

    申请号：US493093

    申请日：1983-05-09

    申请人： Richard C. Eden ,  George R. Kaelin

    发明人： Richard C. Eden ,  George R. Kaelin

    IPC分类号： G11C11/412 ,  G11C11/418 ,  G11C11/419 ,  G11C7/00 ,  G11C11/34

    CPC分类号： G11C11/418 ,  G11C11/412 ,  G11C11/419

    摘要： A random access memory circuit for use with positive and negative supply voltages, a read enable line, an output line, and write "1" and "0" lines includes first, second, third, and fourth level shifting diodes. A first input isolation diode is connected between the write "1" line and the first level shifting diode. A second input isolation diode is connected between the write "0" line and the cathode of the third level shifting diode. The drain of a first write FET is connected to the anode of the third diode, the source is connected to the read enable line, and the gate is connected to the cathode of the second level shifting diode. A second write FET has its drain connected to the anode of the first level shifting diode, its source connected to the read enable line, and its gate connected to the cathode of the fourth diode. An output buffer FET is connected by its source to the read enable line, by its gate to the cathode of the fourth diode. An output isolation diode is connected between the drain of the output buffer FET and the output line.

    摘要翻译： 用于正电源电压和负电源电压的随机存取存储器电路，读使能线，输出线和写“1”和“0”线包括第一，第二，第三和第四电平移位二极管。 第一输入隔离二极管连接在写“1”线和第一电平移位二极管之间。 第二输入隔离二极管连接在写“0”线和第三电平转换二极管的阴极之间。 第一写FET的漏极连接到第三二极管的阳极，源极连接到读使能线，栅极连接到第二电平移位二极管的阴极。 第二写FET的漏极连接到第一电平移位二极管的阳极，其源极连接到读使能线，其栅极连接到第四二极管的阴极。 输出缓冲FET由其源极连接到读使能线，其栅极连接到第四二极管的阴极。 输出隔离二极管连接在输出缓冲FET的漏极和输出线之间。

    Schottky diode FET logic integrated circuit
    8.
    发明授权
    Schottky diode FET logic integrated circuit 失效
    肖特基二极管FET逻辑集成电路

    公开(公告)号：US4300064A

    公开(公告)日：1981-11-10

    申请号：US11266

    申请日：1979-02-12

    申请人： Richard C. Eden

    发明人： Richard C. Eden

    IPC分类号： H03K19/0956 ,  H03K19/094 ,  H03K19/017 ,  H03K19/20

    CPC分类号： H03K19/0956 ,  Y10S331/03

    摘要： A logic circuit is provided which uses Schottky barrier switching diodes to perform the "OR" logic function on logic inputs. The outputs from the switching diodes control the gate of a field-effect transistor (FET) which provides logic inversion and gain. The source of the FET is grounded and its drain provides the output of the logic circuit. Bias current for the switching diodes and gate turn-off current for the FET are provided by a pull down, and a pull up is provided to operate the FET. In a second embodiment, two separate groups of switching diodes control separate gates of a dual-gated FET to provide a two-level "OR/NAND" logic circuit. In a third embodiment, the outputs from a pair of two-level logic circuits are joined to provide a three-level "OR/NAND/WIRED-AND" logic circuit.

    摘要翻译： 提供了使用肖特基势垒开关二极管在逻辑输入上执行“或”逻辑功能的逻辑电路。 开关二极管的输出控制提供逻辑反相和增益的场效应晶体管（FET）的栅极。 FET的源极接地，其漏极提供逻辑电路的输出。 开关二极管的偏置电流和FET的栅极截止电流由下拉提供，并提供上拉来操作FET。 在第二实施例中，两组独立的开关二极管控制双门控FET的分离栅极以提供两级“或”逻辑电路。 在第三实施例中，来自一对两电平逻辑电路的输出被连接以提供三电平“或/非/有线和”逻辑电路。

    Buried channel charge coupled device with semi-insulating substrate
    9.
    发明授权
    Buried channel charge coupled device with semi-insulating substrate 失效
    掩埋沟道电荷耦合器件与半绝缘衬底

    公开(公告)号：US4285000A

    公开(公告)日：1981-08-18

    申请号：US19807

    申请日：1979-03-12

    申请人： Ira Deyhimy ,  Richard C. Eden ,  James S. Harris, Jr. ,  Lucia O. Bubulac

    发明人： Ira Deyhimy ,  Richard C. Eden ,  James S. Harris, Jr. ,  Lucia O. Bubulac

    IPC分类号： H01L29/765 ,  H01L29/78 ,  G11C19/28 ,  H01L29/06 ,  H01L29/56

    CPC分类号： H01L29/765

    摘要： A charge coupled device has a semi-insulating semiconductor for a substrate. Resistivity of the semiconductor is at least 10.sup.6 ohm cm. A semi-conductive layer is grown epitaxially or is implanted on the substrate to form a thin, active, charge transport layer. A row of parallel, closely spaced gates on the charge transport layer provides individual storage wells in the charge transport layer. In a preferred embodiment, ohmic contacts adjacent the first and last gates in the row of gates provide a means for injecting a signal into the charge transport layer and a means for detecting the signal. Preferably, the substrate is semi-insulating GaAs and the gates are Schottky barrier gates.

    摘要翻译： 电荷耦合器件具有用于衬底的半绝缘半导体。 半导体的电阻率至少为106欧姆厘米。 半导体层外延生长或植入到衬底上以形成薄的，有活性的电荷传输层。 在电荷传输层上的一排平行的，紧密间隔的栅极提供电荷输送层中的各个存储阱。 在优选实施例中，邻近栅极行中的第一和第二栅极的欧姆接触提供用于将信号注入电荷传输层的装置和用于检测信号的装置。 优选地，衬底是半绝缘GaAs，栅极是肖特基势垒栅极。