公开(公告)号：US20100109710A1

公开(公告)日：2010-05-06

申请号：US12530583

申请日：2008-03-03

申请人： Richard Morisson

发明人： Richard Morisson

IPC分类号： G11C27/02

CPC分类号： G11C27/024 ,  G11C27/02

摘要： The invention relates to sample-and hold modules, and notably those which are intended to be placed upstream of an analog-digital converter. The sample-and-hold module conventionally comprises a differential pair of transistors, a follower transistor and a storage capacitor. The follower transistor is turned on during a sampling phase by the application of an emitter current by means of a first current switch and can be disabled during a hold phase by the application of a disabling voltage to its base. The sample-and-hold module operates according to the invention with a hold phase beginning at the same time as the end of a sampling phase and terminating before the start of a new sampling phase. Switching spikes are thus avoided at the transition between the end of a hold phase and the start of a new sampling phase.

摘要翻译： 本发明涉及采样和保持模块，特别是涉及放置在模数转换器上游的模块。 采样保持模块通常包括差分对晶体管，随动晶体管和存储电容器。 跟随器晶体管在采样阶段期间通过借助于第一电流开关施加发射极电流而导通，并且可以在保持阶段期间通过向其基极施加禁用电压而被禁用。 采样和保持模块根据本发明进行操作，其中保持阶段从采样阶段结束的同时开始并在新采样阶段开始之前终止。 因此，在保持阶段的结束和新的采样阶段的开始之间的转换中避免了切换尖峰。

公开(公告)号：US07391352B2

公开(公告)日：2008-06-24

申请号：US10575273

申请日：2004-10-13

申请人： Richard Morisson

发明人： Richard Morisson

IPC分类号： H03M1/12

CPC分类号： H03M1/0646 ,  H03M1/365

摘要： The invention pertains to a comparison circuit for an analog/digital converter. In order to reduce the effect of the offset voltages of the various comparators of the comparison circuit, voltage followers and a resistor network delivering at its outputs, mean voltages that are the average of those present on outputs of the comparators are linked downstream of the outputs of the comparators.

摘要翻译： 本发明涉及一种用于模拟/数字转换器的比较电路。 为了减少比较电路的各种比较器的偏移电压，电压跟随器和在其输出端传送的电阻网络的影响，平均电压是比较器输出端的平均电压，连接在输出端的下游 的比较。

公开(公告)号：US4970452A

公开(公告)日：1990-11-13

申请号：US452852

申请日：1989-12-19

申请人： Stephane Barbu ,  Richard Morisson

发明人： Stephane Barbu ,  Richard Morisson

IPC分类号： G05F3/22 ,  G05F1/56 ,  H03K17/66

CPC分类号： H03K17/667

摘要： An integrated circuit comprising a current generator which is switchable to at least two modes. A first stage comprises a current mirror (T.sub.3, T.sub.4) having two branches. A differential pair second stage (T.sub.1, T.sub.2) is either in a balanced state (current output zero) or in an unbalanced state (current source R.sub.10, T.sub.10 supplying a current I.sub.1). In the balanced state a second current source (R.sub.20, T.sub.20) supplies a current which maintains the currents in the two branches of the current mirror constant.

摘要翻译： 一种集成电路，包括可切换至少两种模式的电流发生器。 第一级包括具有两个分支的电流镜（T3，T4）。 差分对第二级（T1，T2）处于平衡状态（电流输出为零）或不平衡状态（电流源R10，提供电流I1的T10）。 在平衡状态下，第二电流源（R20，T20）提供保持电流镜的两个分支中的电流恒定的电流。

公开(公告)号：US08232836B2

公开(公告)日：2012-07-31

申请号：US12866043

申请日：2009-01-28

申请人： Jean-Alain Nicolas ,  Richard Morisson

发明人： Jean-Alain Nicolas ,  Richard Morisson

IPC分类号： H01L25/00

CPC分类号： H03K19/00369

摘要： The invention relates to an integrated circuit comprising a succession of N identical elementary circuits (CE1, CE2, . . . CEN), juxtaposed in the order of their rank j varying from 1 to N, N being at least equal to 50, and all having to receive two reference potentials Vref and V0 supplied by two conductors. An upstream input of the second conductor is situated geographically on the side of the rank 1 of the succession of juxtaposed circuits, and an upstream input of the first conductor is situated geographically on the side of the rank N of the succession of juxtaposed circuits. This reduces the error in the potential difference applied to the elementary circuits all along the succession, an error that originates from the non-zero resistance of the conductors. The integrated circuit is applicable to analog-digital converters or digital-analog converters with high resolution.

摘要翻译： 本发明涉及一种集成电路，其包括一系列相同的基本电路（CE1，CE2，...，CEN），其级数j从1到N，N等于50等于或等于50，并且全部 必须接收由两个导体提供的两个参考电位Vref和V0。 第二导体的上游输入位于地理上位于并排电路序列1的一侧，并且第一导体的上游输入位于地理上位于该并列电路序列N的一侧。 这样可以减少施加到基本电路上的电位差的误差，该误差来自导体的非零电阻。 该集成电路适用于具有高分辨率的模数转换器或数模转换器。

公开(公告)号：US6081214A

公开(公告)日：2000-06-27

申请号：US39760

申请日：1998-03-16

申请人： Richard Morisson ,  Philippe Gandy ,  Frederic Darthenay

发明人： Richard Morisson ,  Philippe Gandy ,  Frederic Darthenay

IPC分类号： H03F3/45 ,  H03M1/10 ,  H03M1/12 ,  H03M1/16 ,  H03M1/76 ,  H03M1/06

CPC分类号： H03F3/45479 ,  H03M1/1028 ,  H03M1/167 ,  H03M1/76

摘要： An A/D conversion device includes: an amplifier AMP provided with regulating means controlled by a control signal OC or GC for adjusting the value of its output voltage V2, andan A/D converter ADC2 intended to convert the output voltage V2 of the amplifier AMP into digital signals.The device includes means S0 or MUX for setting the input of the amplifier AMP at a reference potential when a calibration signal CALOS or CALG is active, and at least a calibration arrangement DEC0 or DECM each havinga module comparing the output of the second converter ADC2 with a predetermined binary word,a module supplying the control signal OC or GC whose value depends on the result of said comparison, andmeans for storing the control signal OC or GC when the corresponding calibration signal CALOS or CALG is inactive.

摘要翻译： A / D转换装置包括：放大器AMP，其具有由用于调节其输出电压V2的值的控制信号OC或GC控制的调节装置;以及用于转换放大器的输出电压V2的A / D转换器ADC2 AMP进入数字信号。 器件包括用于当校准信号CALOS或CALG有效时将放大器AMP的输入设置为参考电位的装置S0或MUX，以及至少校准装置DEC0或DECM，每个具有比较第二转换器ADC2的输出的模块 具有预定的二进制字，提供其值取决于所述比较结果的控制信号OC或GC的模块以及当对应的校准信号CALOS或CALG无效时用于存储控制信号OC或GC的装置。

公开(公告)号：US20060220693A1

公开(公告)日：2006-10-05

申请号：US10570322

申请日：2004-10-15

申请人： Richard Morisson

发明人： Richard Morisson

IPC分类号： G11C27/02

CPC分类号： G11C27/024 ,  G11C27/026

摘要： The invention relates to a blocking sampler intended in particular to be used upstream of a fast analog digital converter. The blocking sampler comprises two main semi-samplers each having a respective differential input (E, E′) and a respective differential output (S, S′). With each main semi-sampler is associated a respective auxiliary blocking semi-sampler comprising an auxiliary tracking transistor (T1a, T1a′) powered by a voltage tapped off from the terminals of the storage capacitor (C′, C) of the other main blocking sampler, an auxiliary storage capacitor (Ca, Ca′) linked to the output of this auxiliary tracking transistor and an auxiliary current switch (T2a, T3a, SC1a; T2′a, T3′a, SC1a′) controlled in synchronism with the current switch of the main blocking sampler so as to authorize or block the passage of current in the auxiliary tracking transistor. The auxiliary samplers serve to improve the sampling dynamics in the cases where the signal to be sampled varies rapidly.

摘要翻译： 本发明涉及一种特别用于在快速模拟数字转换器的上游使用的阻塞采样器。 阻塞采样器包括两个主要的半采样器，每个采样器具有相应的差分输入（E，E'）和相应的差分输出（S，S'）。 对于每个主半采样器，相关联的辅助阻挡半采样器包括由从存储电容器（C'，C）的端子分接的电压供电的辅助跟踪晶体管（T 1 a，T 1 a'） 另一个主阻塞采样器，与该辅助跟踪晶体管的输出端连接的辅助存储电容器（Ca，Ca'）和辅助电流开关（T 2 a，T 3 a，SC 1 a; T 2'a，T 3 'a，SC1a'）与主阻塞采样器的电流开关同步地控制，以便授权或阻止辅助跟踪晶体管中的电流通过。 在采样信号快速变化的情况下，辅助采样器用于提高采样动态。

公开(公告)号：US5805096A

公开(公告)日：1998-09-08

申请号：US764834

申请日：1996-12-12

申请人： Richard Morisson ,  Pieter Vorenkamp

发明人： Richard Morisson ,  Pieter Vorenkamp

IPC分类号： H03M1/20 ,  H03M1/36 ,  H03M1/14

CPC分类号： H03M1/205 ,  H03M1/365

摘要： An A/D converter in which an interpolation circuit (15, 16, 17, 18) makes weighted combinations of reference crossing signals (A/Ac,B/Bc) provided by an input circuit (100, 200), so as to obtain an expanded set of reference crossing signals (A/Ac+A1/Ac1 . . . A7/Ac7, B/Bc+B1/Bc1 . . . Bc7). The interpolation circuit (15, 16, 17, 18) is arranged to make at least one weighted combination of reference crossing signals with weighting factors which have a non-integer ratio so as to compensate for a non-linearity in the reference crossing signals (A/Ac,B/Bc). Accordingly, a better compromise is obtained between accuracy, on the one hand, and circuit complexity, on the other hand.

摘要翻译： 一种A / D转换器，其中内插电路（15,16,17,18）进行由输入电路（100,200）提供的参考交叉信号（A / Ac，B / Bc）的加权组合，以便获得 一组扩展的参考交叉信号（A / Ac + A1 / Ac1 ... A7 / Ac7，B / Bc + B1 / Bc1 ... Bc7）。 插值电路（15,16,17,18）被布置成使参考交叉信号与具有非整数比的加权因子的至少一个加权组合以补偿参考交叉信号中的非线性（ A / Ac，B / Bc）。 因此，另一方面，一方面在精度与电路复杂性之间获得更好的妥协。

公开(公告)号：US5079497A

公开(公告)日：1992-01-07

申请号：US567415

申请日：1990-08-14

申请人： Stephane Barbu ,  Richard Morisson ,  Philippe Gandy

发明人： Stephane Barbu ,  Richard Morisson ,  Philippe Gandy

IPC分类号： G05F1/56 ,  G05F1/565

CPC分类号： G05F1/565 ,  Y10S323/901

摘要： The invention relates to a circuit intended to supply a reference voltage comprising a voltage generator (REF) provided with a supply terminal and an output for supplying a voltage having a given nominal value (V.sub.R) and comprising a differential amplifier (A), fed by a first supply voltage, whose non-inverting input is connected to the output of the voltage generator (REF). An output of the differential amplifier (A) is connected to an input of a follower stage (T) through a controlled switching device (1), the follower stage (T) having its input connected to the first supply voltage through a first resistor (R.sub.1) and having its output, which supplies the said reference voltage (V.sub.D), connected on the one hand to the inverting input of the differential amplifier (A) through a divider bridge and on the other hand to the supply termianl of the voltage generator (REF). A control circuit (C) of the switching device is operated so as to receive at least the supply voltage in such a manner that the switching device (1) is closed when the supply voltage reaches a threshold for which both the voltage generator and the differential amplifier are in a nominal operating zone.

摘要翻译： 本发明涉及一种旨在提供参考电压的电路，该电路包括设置有电源端子的电压发生器（REF）和用于提供具有给定额定值（VR）的电压并且包括差分放大器（A）的输出的输出，该差分放大器 第一电源电压，其非反相输入端连接到电压发生器（REF）的输出端。 差分放大器（A）的输出通过受控开关器件（1）连接到跟随器级（T）的输入端，所述跟随器级（T）的输入端通过第一电阻器 R1），并且其输出端通过分压桥将所述参考电压（VD）提供给差分放大器（A）的反相输入，另一方面连接到电压发生器的电源端 （REF）。 操作开关装置的控制电路（C），以便至少接收电源电压，使得当电源电压达到电压发生器和差动器的阈值时，开关装置（1）闭合 放大器处于标称工作区。

公开(公告)号：US20070241953A1

公开(公告)日：2007-10-18

申请号：US10575273

申请日：2004-10-13

申请人： Richard Morisson

发明人： Richard Morisson

IPC分类号： H03M1/36

CPC分类号： H03M1/0646 ,  H03M1/365

摘要： The invention pertains to a comparison circuit for an analog/digital converter. In order to reduce the effect of the offset voltages of the various comparators of the comparison circuit, voltage followers and a resistor network delivering at its outputs, mean voltages that are the average of those present on outputs of the comparators are linked downstream of the outputs of the comparators.

摘要翻译： 本发明涉及一种用于模拟/数字转换器的比较电路。 为了减少比较电路的各种比较器的偏移电压，电压跟随器和在其输出端传送的电阻网络的影响，平均电压是比较器输出端存在的平均电压，连接在输出端的下游 的比较。

公开(公告)号：US06191816B1

公开(公告)日：2001-02-20

申请号：US08988598

申请日：1997-12-11

申请人： Frédéric Darthenay ,  Richard Morisson

发明人： Frédéric Darthenay ,  Richard Morisson

IPC分类号： H04N5217

CPC分类号： H04N5/185

摘要： The invention relates to an interface circuit FE intended to receive a pseudo-periodical input signal Vin having a reference level and a video level, and to supply a signal Vs having a level which is representative of the difference between the reference level and the video level, said interface circuit comprising: two sampling branches BR1 and BR2 simultaneously supplying the reference level and the video level, and a subtracter SUB having inputs which receive the outputs of the branches BR1 and BR2. According to the invention, the inputs of the branches BR1 and BR2 are jointly connected via a first capacitance C1 to the input of the interface circuit FE, which comprises control means CM allowing adjustment of the values of the signals at the inputs of the subtracter SUB so that they are equal when they are representative of one and the same reference level.

摘要翻译： 本发明涉及一种用于接收具有参考电平和视频电平的伪周期输入信号Vin的接口电路FE，并且提供具有代表参考电平和视频电平之间的差的电平的信号Vs 所述接口电路包括：同时提供参考电平和视频电平的两个采样分支BR1和BR2，以及具有接收分支BR1和BR2的输出的输入的减法器SUB。根据本发明，分支BR1和 BR2经由第一电容C1共同连接到接口电路FE的输入端，该接口电路FE包括控制装置CM，其允许调节减法器SUB的输入处的信号值，使得它们在代表一个和 相同的参考水平。