公开(公告)号：US08391077B2

公开(公告)日：2013-03-05

申请号：US12875662

申请日：2010-09-03

申请人： Rieko Tanaka ,  Koichi Fukuda

发明人： Rieko Tanaka ,  Koichi Fukuda

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/06 ,  G11C16/32 ,  G11C16/3418

摘要： Nonvolatile semiconductor memory device according to one embodiment includes: a plurality of planes; a memory cell array provided in the plurality of planes respectively; bit lines; and a control circuit. Each memory cell array is configured as an array of NAND cell units each including a memory string. The memory string includes a plurality of nonvolatile memory cells connected in series. The bit lines are connected to a first end of the NAND cell units, respectively. The control circuit controls a write operation of charging the bit lines up to a certain voltage value, and then setting data in the nonvolatile memory cells to a certain threshold voltage distribution state. The control circuit is configured to be capable of executing an operation of charging the bit lines in a write operation by varying timings of starting charging the bit lines among the plurality of planes.

摘要翻译： 根据一个实施例的非易失性半导体存储器件包括：多个平面; 分别设置在所述多个平面中的存储单元阵列; 位线 和控制电路。 每个存储单元阵列被配置为每个包括存储器串的NAND单元阵列的阵列。 存储器串包括串联连接的多个非易失性存储单元。 位线分别连接到NAND单元单元的第一端。 控制电路控制对位线充电达一定电压值的写入操作，然后将非易失性存储单元中的数据设置到一定的阈值电压分布状态。 控制电路被配置为能够通过改变开始对多个平面中的位线充电的定时来执行在写入操作中对位线进行充电的操作。

公开(公告)号：US08254168B2

公开(公告)日：2012-08-28

申请号：US12820342

申请日：2010-06-22

申请人： Yuya Suzuki ,  Rieko Tanaka

发明人： Yuya Suzuki ,  Rieko Tanaka

IPC分类号： G11C11/34

CPC分类号： G11C16/26 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3459 ,  G11C2211/5621

摘要： According to one embodiment, a semiconductor device includes memory cells, bit lines, a write circuit, and sense amplifiers. The bit lines are connected to the memory cells. The sense amplifiers are configured to bias the bit line to which the selected memory cell is connected, to a first voltage until the threshold of the selected memory cell reaches the value of a first write state. Then, when the threshold of the selected memory cell reaches the value of the first write state, the bit line is biased to a second voltage higher than the first voltage. When the threshold of the selected memory cell reaches the value of a second write state, the bit line is continuously biased to a third voltage higher than the second voltage. Bit lines connected to unselected memory cells corresponding to the memory cells other than the selected one are biased to the third voltage.

摘要翻译： 根据一个实施例，半导体器件包括存储器单元，位线，写入电路和读出放大器。 位线连接到存储单元。 感测放大器被配置为将所选择的存储器单元所连接的位线偏置到第一电压，直到所选存储器单元的阈值达到第一写入状态的值。 然后，当所选择的存储单元的阈值达到第一写入状态的值时，位线被偏置到高于第一电压的第二电压。 当所选存储单元的阈值达到第二写入状态的值时，位线被连续地偏置到高于第二电压的第三电压。 连接到与所选存储单元不同的存储单元的未选择存储单元的位线被偏置到第三电压。

公开(公告)号：US20110063915A1

公开(公告)日：2011-03-17

申请号：US12723960

申请日：2010-03-15

申请人： Rieko TANAKA ,  Takumi Abe

发明人： Rieko TANAKA ,  Takumi Abe

IPC分类号： G11C16/04 ,  G11C16/06 ,  G11C7/00

CPC分类号： G11C16/24 ,  G11C16/32

摘要： A non-volatile semiconductor memory device includes a memory cell array having a plurality of non-volatile memory cells capable electrically rewriting data, bit lines and source lines. A driver circuit is coupled with the source lines of the memory cell array to output a voltage higher than a power source voltage or a programming voltage for writing data in the memory cell by switching over, and the driver circuit discharges the source lines to ground. A sense amplifier circuit is coupled with the bit line and reads out the data in the memory cell. The sense amplifier includes a sense node and a capacitor having first and second terminals, and the first terminal is coupled with the sense node. The sense node is boosted by a plurality of voltages applied to the second terminal of the capacitor.

摘要翻译： 非易失性半导体存储器件包括具有能够电重写数据，位线和源极线的多个非易失性存储单元的存储单元阵列。 驱动电路与存储单元阵列的源极线耦合，以输出高于电源电压或编程电压的电压，用于通过切换将数据写入存储单元，并且驱动电路将源极线放电到地。 读出放大器电路与位线耦合并读出存储器单元中的数据。 感测放大器包括感测节点和具有第一和第二终端的电容器，并且第一端子与感测节点耦合。 感测节点被施加到电容器的第二端子的多个电压升压。

公开(公告)号：US06492392B1

公开(公告)日：2002-12-10

申请号：US09481542

申请日：2000-01-12

申请人： Yutaka Kanda ,  Rieko Tanaka ,  Mitsunobu Hara ,  Jun Eishima ,  Shiro Akinaga ,  Tadashi Ashizawa

发明人： Yutaka Kanda ,  Rieko Tanaka ,  Mitsunobu Hara ,  Jun Eishima ,  Shiro Akinaga ,  Tadashi Ashizawa

IPC分类号： A61K31445

CPC分类号： C07D401/14 ,  C07D231/12 ,  C07D233/56 ,  C07D249/08 ,  C07D401/06 ,  C07D405/14 ,  C07D409/14

摘要： The present invention provides 2-piperidone compounds or pharmaceutically acceptable salts thereof, which have a potent activity of inhibiting the proliferation of tumor cells and thus are useful as medicaments, as well as antitumor agents containing these compounds. The 2-piperidone compound is represented by the following formula (I): wherein R1 represents —(CH2)nR1a {wherein n is an integer of from 0 to 5, and R1a represents amino, lower alkylamino, di(lower alkyl)amino, substituted or unsubstituted aryl, or a substituted or unsubstituted heterocyclic group}, and R2 and R3 independently represent lower alkyl which may be substituted by lower alkoxycarboyl; lower alkenyl, aralkyl or lower alkynyl which may be substituted by substituted or unsubstituted aryl or a substituted or unsubstituted heterocyclic group; substituted or unsubstituted aryl; or a substituted or unsubstituted heterocyclic group.

摘要翻译： 本发明提供了具有抑制肿瘤细胞增殖的有效活性的2-哌啶酮化合物或其药学上可接受的盐，因此可用作药物，以及含有这些化合物的抗肿瘤剂。 2-哌啶酮化合物由下式（I）表示：其中R1表示 - （CH2）nR1a {其中n为0-5的整数，R1a表示氨基，低级烷基氨基，二（低级烷基）氨基，取代的 或未取代的芳基，或取代或未取代的杂环基}，R2和R3独立地表示可以被低级烷氧基羰基取代的低级烷基; 可被取代或未取代的芳基或取代或未取代的杂环基取代的低级烯基，芳烷基或低级炔基; 取代或未取代的芳基; 或取代或未取代的杂环基。

公开(公告)号：US20120163095A1

公开(公告)日：2012-06-28

申请号：US13332682

申请日：2011-12-21

申请人： Rieko TANAKA

发明人： Rieko TANAKA

IPC分类号： G11C16/10

CPC分类号： G11C16/3459

摘要： A semiconductor memory device includes a plurality of bit lines connected to memory cells; a sense amplifier connected to the plurality of bit lines; a memory unit configured to hold failure data of the bit lines; and a controller configured to perform control such that if it is judged that there is a failure in a second bit line adjacent to a first bit line selected in writing data on the basis of the failure data for the bit lines, the potential of the second bit line is set to a first potential in at least any one of programming and verification.

摘要翻译： 半导体存储器件包括连接到存储器单元的多个位线; 连接到所述多个位线的读出放大器; 存储单元，被配置为保存位线的故障数据; 以及控制器，被配置为执行控制，使得如果根据位线的故障数据判断在写入数据时选择的与第一位线相邻的第二位线中存在故障，则第二位线的电位 在编程和验证中的至少任何一个中将位线设置为第一电位。

公开(公告)号：US08081518B2

公开(公告)日：2011-12-20

申请号：US12974065

申请日：2010-12-21

申请人： Rieko Tanaka ,  Koichi Fukuda ,  Takumi Abe

发明人： Rieko Tanaka ,  Koichi Fukuda ,  Takumi Abe

IPC分类号： G11C16/04

CPC分类号： G11C16/26 ,  G11C16/0483

摘要： A semiconductor memory device includes a sense amplifier which senses identical multilevel data, which is stored in a memory cell, a plurality of number of times at a time of read, and a n-channel MOS transistor which has a current path one end of which is connected to the sense amplifier and the other end of which is connected to a bit line. The device further include a control unit which applies a first voltage to a gate electrode of the n-channel MOS transistor, thereby setting the n-channel MOS transistor in an ON state, and applies a second voltage which is higher than the first voltage, to the gate electrode during a period after first sense and before second sense.

公开(公告)号：US08054683B2

公开(公告)日：2011-11-08

申请号：US12563566

申请日：2009-09-21

申请人： Rieko Tanaka ,  Takumi Abe

发明人： Rieko Tanaka ,  Takumi Abe

IPC分类号： G11C16/04

CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

摘要： A semiconductor memory device includes a plurality of memory cells, signal lines, and a control unit. Each of the plurality of memory cells includes a charge storage layer. Each of the plurality of memory cells includes a control gate and is configured to hold two-or-higher-level data. Each of signal lines is electrically connected with a gate or one end of a current path of each of the memory cells. Each of signal lines has a line width which differs depending on each interval between the memory cells adjacent to each other. The control unit controls a voltage applied to each of the signal lines in accordance with the line width of each of the signal lines.

摘要翻译： 半导体存储器件包括多个存储单元，信号线和控制单元。 多个存储单元中的每一个包括电荷存储层。 多个存储器单元中的每一个包括控制栅极，并且被配置为保持两级或更高级别的数据。 每个信号线与每个存储单元的电流路径的栅极或一端电连接。 每个信号线具有根据彼此相邻的存储单元之间的每个间隔而不同的线宽。 控制单元根据每个信号线的线宽来控制施加到各信号线的电压。

公开(公告)号：US07872919B2

公开(公告)日：2011-01-18

申请号：US12493680

申请日：2009-06-29

申请人： Rieko Tanaka ,  Koichi Fukuda ,  Takumi Abe

发明人： Rieko Tanaka ,  Koichi Fukuda ,  Takumi Abe

IPC分类号： G11C16/06

CPC分类号： G11C16/26 ,  G11C16/0483

摘要： A semiconductor memory device includes a sense amplifier which senses identical multilevel data, which is stored in a memory cell, a plurality of number of times at a time of read, and a n-channel MOS transistor which has a current path one end of which is connected to the sense amplifier and the other end of which is connected to a bit line. The device further include a control unit which applies a first voltage to a gate electrode of the n-channel MOS transistor, thereby setting the n-channel MOS transistor in an ON state, and applies a second voltage which is higher than the first voltage, to the gate electrode during a period after first sense and before second sense.

摘要翻译： 一种半导体存储器件包括读出放大器，该读出放大器在读取时感测存储在存储器单元中的多个相同的多电平数据，多个次数的n沟道MOS晶体管以及其一端的电流路径 连接到读出放大器，另一端连接到位线。 该装置还包括控制单元，其向n沟道MOS晶体管的栅电极施加第一电压，从而将n沟道MOS晶体管设置为导通状态，并施加高于第一电压的第二电压， 在第一感测之后的时段期间和第二感测之前的栅电极。

公开(公告)号：US08836010B2

公开(公告)日：2014-09-16

申请号：US13344765

申请日：2012-01-06

申请人： Koichi Fukuda ,  Rieko Tanaka ,  Takumi Abe

发明人： Koichi Fukuda ,  Rieko Tanaka ,  Takumi Abe

IPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/105 ,  H01L49/02

CPC分类号： H01L27/11531 ,  H01L27/105 ,  H01L27/11526 ,  H01L28/24

摘要： A nonvolatile semiconductor memory device including a memory cell configured to store data and a resistor element provided around the memory cell. The memory cell includes a charge storage layer provided above a substrate, a first semiconductor layer formed on a top surface of the charge storage layer via an insulating layer, and a first low resistive layer formed on a top surface of the first semiconductor layer and having resistance lower than that of the first semiconductor layer. The resistor element includes a second semiconductor layer formed on the same layer as the first semiconductor layer, and a second low resistive layer formed on the same layer as the first low resistive layer and on a top surface of the second semiconductor layer, having resistance lower than that of the second semiconductor layer.

摘要翻译： 一种非易失性半导体存储器件，包括被配置为存储数据的存储单元和设置在存储单元周围的电阻元件。 存储单元包括设置在基板上的电荷存储层，经由绝缘层形成在电荷存储层的顶表面上的第一半导体层和形成在第一半导体层的顶表面上的第一低电阻层，并且具有 电阻低于第一半导体层的电阻。 电阻元件包括形成在与第一半导体层相同的层上的第二半导体层，以及形成在与第一低电阻层相同的层上的第二低电阻层，以及形成在第二半导体层的顶表面上的第二低电阻层， 比第二半导体层的厚度大。

公开(公告)号：US08284605B2

公开(公告)日：2012-10-09

申请号：US12978878

申请日：2010-12-27

申请人： Rieko Tanaka ,  Makoto Iwai

发明人： Rieko Tanaka ,  Makoto Iwai

IPC分类号： G11C11/34

CPC分类号： G11C16/0408 ,  G11C16/26

摘要： An embodiment of the invention provides a semiconductor storage device including a NAND string, a SEN node, and a capacitor. The NAND string includes plural series-connected memory cells, and one end of the NAND string is connected to a bit line while the other end is connected to a common source line. The SEN node is configured to be able to be electrically connected to a voltage source and the bit line. In the capacitor, one end is connected to the SEN node while the other end is connected to a CLK node to which a voltage within a predetermined range is applied. A discharge rate of the SEN node is enhanced by decreasing a capacitance during discharge of the SEN node only when a selected memory cell selected from the plural memory cells is an on-cell.

摘要翻译： 本发明的实施例提供一种包括NAND串，SEN节点和电容器的半导体存储装置。 NAND串包括多个串联存储单元，并且NAND串的一端连接到位线，而另一端连接到公共源极线。 SEN节点被配置为能够电连接到电压源和位线。 在电容器中，一端连接到SEN节点，而另一端连接到施加了预定范围内的电压的CLK节点。 只有当从多个存储单元中选择的所选择的存储单元是开小区时，通过减少SEN节点的放电期间的电容来增强SEN节点的放电率。