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1.发明授权
公开(公告)号：US5691652A
公开(公告)日：1997-11-25
申请号：US603977
申请日：1996-02-20
IPC分类号： H01L27/04 , H01L21/822 , H03K3/356 , H03K19/00 , H03K19/003 , H03K19/096 , H03K17/16
CPC分类号： H03K19/00338 , H03K3/35606
摘要： A system and method for improving alpha-particle induced soft error rates in integrated circuits is provided. Logic isolation circuits implemented using a substantially fewer number of pn-junctions are situated at the outputs of fast logic portions containing a substantially greater number of pn-junctions. The present invention reduces the vulnerability of a dynamic logic circuit of incurring alpha soft errors by effectively trading the probability of an isolation circuit composed of only a few pn-junctions incurring alpha-particle strikes with the probability of a fast logic circuit having substantially more pn-junctions incurring alpha-particle strikes. By reducing the number of pn-junctions susceptible to alpha-particle strikes, the present invention significantly lowers the potential alpha-particle induced soft error rate. In one embodiment, isolation circuits used in the present invention are implemented using self-timed logic, to reduce the window in which a circuit is logically vulnerable to alpha strikes, in which a loss of state can occur.
摘要翻译： 提供了一种用于提高集成电路中α粒子诱导的软错误率的系统和方法。 使用基本上较少数量的pn结实现的逻辑隔离电路位于包含基本上更多数量的pn结的快速逻辑部分的输出处。 本发明通过有效地交换由仅具有几个pn结组成的隔离电路的概率来降低产生阿尔法软错误的动态逻辑电路的脆弱性，其中快速逻辑电路具有基本上更多的pn的概率 - 引起α粒子撞击的结点。 通过减少易受α-粒子撞击的pn结的数量，本发明显着降低了潜在的α粒子诱导的软错误率。 在一个实施例中，本发明中使用的隔离电路使用自定时逻辑来实现，以减少电路逻辑上容易受到可能发生状态损失的α打击的窗口。
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2.发明授权
公开(公告)号：US5740087A
公开(公告)日：1998-04-14
申请号：US656125
申请日：1996-05-31
CPC分类号： G06F9/3836 , G06F1/3203 , G06F1/3287 , G06F9/3867 , G06F9/3869 , Y02B60/1282
摘要： An apparatus and method are disclosed for regulating power consumption in a digital system of the kind including at least one triggerable functional block that consumes more power when triggered than when not triggered. In an embodiment for use with a digital system that includes a pipeline of such triggerable functional blocks, a state machine sequentially applies trigger pulses to each of the functional blocks in the pipeline whenever the output of an OR gate is asserted. It does so by generating a series of enable signals that are used to gate a clock signal to the trigger inputs of the functional blocks. The state machine includes a series of storage devices having outputs. Outputs of the storage devices are used to provide the enable signals. The inputs of the OR gate are coupled to a start signal that indicates when the functional blocks should be triggered to process data, and also to a dummy start signal that indicates when the functional blocks should be triggered to maintain power consumption. Outputs from the storage devices are also used to indicate the number of times the pipeline has been triggered during a recent number of clock cycles. A programmable register is used to store a data value corresponding to the minimum desired level of power consumption for the pipelined functional blocks. The dummy start signal is generated by combinational logic whose inputs include the outputs of the storage devices and the data value. Because the minimum desired level of power consumption may be programmed by the user, thermal characterization and balancing of step load with average power are facilitated.
摘要翻译： 公开了一种用于调节这种类型的数字系统中的功率消耗的装置和方法，包括当触发时比不触发时消耗更多功率的至少一个可触发功能块。 在包括这种可触发的功能块的流水线的数字系统的一个实施例中，状态机在每个OR门的输出被断言的情况下，在流水线中的每个功能块上顺序地施加触发脉冲。 它通过产生用于将时钟信号门控到功能块的触发输入的一系列使能信号来实现。 状态机包括具有输出的一系列存储装置。 存储设备的输出用于提供使能信号。 或门的输入耦合到起始信号，该启动信号指示何时触发功能块以处理数据，以及指示何时触发功能块以维持功耗的虚拟启动信号。 来自存储设备的输出也用于指示在最近数量的时钟周期期间流水线被触发的次数。 可编程寄存器用于存储对应于流水线功能块的最小期望功耗水平的数据值。 虚拟启动信号由组合逻辑产生，其输入包括存储设备的输出和数据值。 由于用户可以编程所需的最小功耗水平，因此易于平均功率的步进负载的热表征和平衡。
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3.发明授权Microbicidal compositions and methods using combinations of propiconazole and N-alkyl heterocycles and salts thereof 失效使用丙环唑和N-烷基杂环的组合的杀菌组合物和方法及其盐公开(公告)号：US06576629B1
公开(公告)日：2003-06-10
申请号：US09369298
申请日：1999-08-06
申请人： David Oppong , Marilyn S. Whittemore , M. Sheldon Ellis , Robert H. Miller, Jr. , Xiaugdong Zhou , Michael E. Elmore
发明人： David Oppong , Marilyn S. Whittemore , M. Sheldon Ellis , Robert H. Miller, Jr. , Xiaugdong Zhou , Michael E. Elmore
IPC分类号： A61K31535
CPC分类号： A01N43/653 , A01N43/84 , A01N43/80 , A01N43/76 , A01N43/50 , A01N43/46 , A01N43/40 , A01N43/36 , A01N2300/00
摘要： A method for increasing the effectiveness of the microbicide propiconazole, (RS)-1-2-[(2,4-dichlorophenyl)-2-propyl-1,3-dioxalan-2ylmethyl]-1H-1,2,4-triazole, is described. In the method, propiconazole and a potentiator, an N-alkyl heterocyclic compound, its salt, or a mixture thereof, are applied to a substrate or aqueous system subject to the growth of microorganisms. The N-alkyl heterocyclic compound, its salt, or a mixture thereof is applied in an amount effective to increase the microbicidal activity of the microbicide. The N-alkyl heterocyclic compound has the formula: The variable “n” ranges from 5 to 17, and the heterocyclic ring defined by is a substituted or unsubstituted ring having four to eight members. Microbicidal compositions are described where propiconazole and an N-alkyl heterocyclic compound, its salt, or a mixture thereof are present in a combined amount: effective to control the growth of at least one microorganism. Methods for controlling the growth of microorganisms on various substrates and in various aqueous systems are also described. The combination of propiconazole and an N-alkyl heterocyclic compound, its salt, or a mixture thereof is particularly useful as microbicidal in the leather industry, the lumber industry, the papermaking industry, the textile industry, the agricultural industry, and the coating industry, as well as in industrial process waters.
摘要翻译： 提高杀微生物剂丙环唑（RS）-1-2 - [（2,4-二氯苯基）-2-丙基-1,3-二氧杂环戊烷-2-基甲基] -1H-1,2,4-三唑的有效性的方法 ，被描述。 在该方法中，将丙环唑和增效剂，N-烷基杂环化合物，其盐或其混合物施加到受微生物生长影响的底物或水性体系上。 以有效提高杀微生物剂的杀菌活性的量施用N-烷基杂环化合物，其盐或其混合物。 N-烷基杂环化合物具有下式：变量“n”为5至17，并且由取代或未取代的环具有四至八个成员所定义的杂环。 描述了杀微生物组合物，其中丙环唑和N-烷基杂环化合物，其盐或其混合物以有效控制至少一种微生物生长的组合量存在。 还描述了控制各种底物和各种水性体系中微生物生长的方法。 丙环唑和N-烷基杂环化合物，其盐或其混合物的组合在皮革工业，木材工业，造纸工业，纺织工业，农业和涂料工业中特别可用作杀菌剂， 以及工业过程水域。
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公开(公告)号：US5889979A
公开(公告)日：1999-03-30
申请号：US653645
申请日：1996-05-24
CPC分类号： H03K3/356165 , G06F9/3869
摘要： A system and method for transferring data between alternately evaluated first and second logic blocks of a dynamic logic pipeline. Associated with the system and method is a transparent data-triggered pipeline latch for controlling data flow between the first and second logic blocks. During an evaluation period accorded the first logic block, data existing at the logic block's data inputs is evaluated. Substantially simultaneously, the data-triggered latch is reset. As valid data is output from the first logic block, the latch is triggered. Immediately after the latch has been triggered, and before a clock-triggered evaluation period is accorded the second logic block, the data stored in the latch is output to the second logic block. Propagation of the early arriving data may be halted by ANDing the early arriving data signals with clocked signals which remain invalid. The invalid signals may comprise clock or data signals. Early arriving data is beneficial when supplied to static logic gates, or when transmitted through heavily loaded data lines which are associated with a propagation delay. A preferred embodiment of the latch comprises high and low level mousetrap data controls. Each control is coupled with a respective high or low level mousetrap data input, output, and storage node, and further comprises an input trigger, an input trigger disabler, a data storage device, a reset mechanism, and a reset disabler. The latch allows data to be driven out when valid, rather than in response to a clock edge.
摘要翻译： 一种用于在动态逻辑管线的交替评估的第一和第二逻辑块之间传送数据的系统和方法。 与系统和方法相关联的是用于控制第一和第二逻辑块之间的数据流的透明数据触发流水线锁存器。 在给定第一逻辑块的评估期间，评估存在于逻辑块的数据输入端的数据。 基本同时，数据触发锁存器被复位。 当有效数据从第一个逻辑块输出时，锁存器被触发。 在锁存器被触发之后，并且在时钟触发的评估周期被赋予第二逻辑块之前，存储在锁存器中的数据被输出到第二逻辑块。 早期到达数据的传播可以通过将早期到达的数据信号与保持无效的时钟信号进行AND运算而停止。 无效信号可以包括时钟或数据信号。 提供给静态逻辑门，或通过与传播延迟相关联的重载数据线传输时，提前到达的数据是有益的。 锁存器的优选实施例包括高和低电平的捕鼠器数据控制。 每个控制与相应的高或低级捕鼠器数据输入，输出和存储节点耦合，并且还包括输入触发器，输入触发器，数据存储设备，复位机构和复位禁用器。 锁存器允许数据在有效时被驱出，而不是响应于时钟边沿。
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公开(公告)号：US5224208A
公开(公告)日：1993-06-29
申请号：US494708
申请日：1990-03-16
CPC分类号： G06T15/04
摘要： A method and apparatus for performing the majority of texture map gradient calculations once per polygon so as to increase processing speed in a graphics system. Texture values are identified for each vertex of an input polygon and are interpolated over the polygon in perspective space in order to find the corresponding values at a given pixel within the polygon. The perspective values of the vertices are linearly interpolated across the polygon to determine the value at the given pixel. The texture gradients are then calculated by defining vectors perpendicular and parallel to the horizon of the plane containing the input polygon so that the resulting components may be calculated. The resulting value is the texture gradient, which may then be used to address a texture map to determine the pre-filtered texture value for that point. A hardware implementation performs the necessary calculations for each pixel in the input polygon. The invention so arranged removes artifacts in the texture mapped image at a low cost and at a high speed.
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6.发明授权Clocking systems and methods for pipelined self-timed dynamic logic circuits 失效用于流水线自定时动态逻辑电路的时钟系统和方法
公开(公告)号：US5434520A
公开(公告)日：1995-07-18
申请号：US885800
申请日：1992-05-19
IPC分类号： G06F7/50 , G06F7/501 , G06F9/38 , G06F15/78 , H03K19/094 , H03K19/096 , H03K19/21 , H03K19/00
CPC分类号： G06F7/5016 , G06F15/8053 , G06F9/3869 , H03K19/094 , H03K19/0966 , H03K19/215
摘要： Clocking systems and methods of the present invention use two or more different clock signals for respective groups or stages of self-timed dynamic (or mousetrap) logic gates. Each clock signal defines a precharging time interval and an evaluation time interval for its respective group or stage of self-timed dynamic logic gates. Using the two or more different clock signals, pipelining of the groups or stages of the self-timed dynamic logic gates can be performed.
摘要翻译： 本发明的时钟系统和方法使用两个或多个不同的时钟信号用于自定时动态（或捕鼠器）逻辑门的各个组或多个阶段。 每个时钟信号为其相应的组或阶段的自定时动态逻辑门定义预充电时间间隔和评估时间间隔。 使用两个或多个不同的时钟信号，可以执行自定时动态逻辑门的组或级的流水线化。
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公开(公告)号：US5390134A
公开(公告)日：1995-02-14
申请号：US11447
申请日：1993-01-29
CPC分类号： G06F7/485 , G06F7/49947
摘要： A rounding means is associated with a carry propagate adder of a floating point processor in order to reduce latency and enhance performance. The rounding mechanism performs a rounding function approximately simultaneously with an addition function performed by the carry propagate adder on fraction inputs FA, FB to ultimately derive a resultant fraction FR, thereby eliminating the need for a conventional post-normalize incrementer. The rounding mechanism has a carry select adder and rounding logic network. The rounding logic network communicates with the carry propagate adder and the carry select adder in order to provide rounding information to the carry select adder. The carry select adder and the rounding logic network jointly provide a rounded output, which is then normalized by the normalizer to thereby derive the resultant fraction.
摘要翻译： 舍入装置与浮点处理器的进位传播加法器相关联，以便减少等待时间并提高性能。 舍入机构与分数输入FA，FB上由进位传播加法器执行的加法函数大致同时执行舍入函数，以最终导出合成分数FR，从而消除对常规后归一化增量器的需要。 舍入机制具有进位选择加法器和舍入逻辑网络。 四舍五入逻辑网络与进位传播加法器和进位选择加法器通信，以便向进位选择加法器提供舍入信息。 进位选择加法器和舍入逻辑网络联合提供舍入输出，然后由归一化器对其进行归一化，从而导出所得分数。
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8.发明授权
公开(公告)号：US5317204A
公开(公告)日：1994-05-31
申请号：US885797
申请日：1992-05-19
IPC分类号： G06F7/38 , G06F7/50 , G06F7/52 , G06F7/527 , G06F7/53 , H03K19/094 , H03K19/096 , H03K19/21 , H03K19/017
CPC分类号： H03K19/094 , G06F7/501 , G06F7/5016 , G06F7/5338 , H03K19/0966 , H03K19/215 , G06F2207/3872
摘要： The adverse effects of charge sharing in dynamic logic gates are mitigated. The dynamic logic gates have an inverting buffer for providing a gate output, an arming mechanism for precharging the inverting buffer input, and ladder logic for receiving a gate input and for discharging the inverting buffer input to ground. The ladder logic comprises a plurality of transistors connected in ladder-like manner. In a first embodiment, the interstitial space between parallel transistor gates in the ladder logic is reduced so as to minimize parasitic capacitances. In a second embodiment, the parasitic capacitance of at a converging node defined by at least three converging transistors is minimized by disposing the transistor gates adjacent one another so that the transistors share a common interstitial space with a region of each transistor gate adjacent a region of each of the other remaining gates. In a third embodiment, a precharger is disposed to inject charge at the converging node when the inverting buffer input is precharged by the arming mechanism. Finally, in a fourth embodiment, the plurality of transistors in the ladder logic are connected in a ladder-like manner exclusively to thereby define a plurality of mutually exclusive paths to ground.
摘要翻译： 动态逻辑门电荷共享的不利影响得到缓解。 动态逻辑门具有用于提供栅极输出的反相缓冲器，用于对反相缓冲器输入进行预充电的布防机构，以及用于接收栅极输入并用于将反相缓冲器输入端接地的电路的梯形逻辑。 梯形逻辑包括以梯状方式连接的多个晶体管。 在第一实施例中，梯形逻辑中的并联晶体管栅极之间的间隙空间被减小，以便最小化寄生电容。 在第二实施例中，由至少三个会聚晶体管限定的会聚节点处的寄生电容通过将晶体管栅极彼此相邻布置而最小化，使得晶体管与每个晶体管栅极的区域共享共同的间隙空间， 每个其他剩下的门。 在第三实施例中，设置预充电器以在反相缓冲器输入被布防机构预充电时在会聚节点处注入电荷。 最后，在第四实施例中，梯形逻辑中的多个晶体管以梯形方式连接，从而限定了多个相互排斥的接地路径。
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公开(公告)号：US07401108B2
公开(公告)日：2008-07-15
申请号：US10946407
申请日：2004-09-21
摘要： A random noise signal generator circuit comprising a random noise source that produces a random noise signal, an amplification circuit that amplifies the random noise signal to produce an amplified random noise signal, a feedback loop having a DC offset correction circuit, and a summer. The DC offset correction circuit processes a fed back portion of the amplified random noise signal to produce a DC offset correction signal. The summer sums the random noise signal produced by the random noise source and the DC offset correction signal to produce a summed signal. The summer is electrically coupled to the amplification circuit for providing the summed signal to the amplification circuitry. The amplification circuitry amplifies the summed signal to produce a random noise output signal.
摘要翻译： 包括产生随机噪声信号的随机噪声源的随机噪声信号发生器电路，放大随机噪声信号以产生放大的随机噪声信号的放大电路，具有DC偏移校正电路的反馈回路和加法器。 DC偏移校正电路处理放大的随机噪声信号的反馈部分以产生DC偏移校正信号。 夏季对由随机噪声源产生的随机噪声信号和DC偏移校正信号进行求和，以产生求和信号。 夏季电耦合到放大电路，用于将加和信号提供给放大电路。 放大电路放大求和信号以产生随机噪声输出信号。
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公开(公告)号：US5754458A
公开(公告)日：1998-05-19
申请号：US655581
申请日：1996-05-30
CPC分类号： G06F7/74 , G06F7/485 , G06F7/49952
摘要： A method and apparatus for determining the trailing bit position from a two operand addition is described. The determination of the trailing bit occurs in parallel with the addition. The two operands are encoded together and the encoded word used to determine the trailing bit position. As the operations of encoding the operands and operating upon the encoded operands require no more time than known methods to determine the trailing bit position after the addition is completed, and as the encoding and operating on the encoded words occurs in parallel with the addition operation, the present invention allows faster processing in the floating point unit.
摘要翻译： 描述用于从两个操作数加法确定尾随位位置的方法和装置。 尾部位的确定与加法并行发生。 两个操作数被编码在一起，并且编码的字用于确定尾随位位置。 由于对编码操作数进行编码并对编码的操作数进行操作的操作不需要比已知方法更多的时间来确定加法完成之后的尾部位位置，并且随着编码字的编码和操作与加法运算并行发生， 本发明允许在浮点单元中更快的处理。
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