公开(公告)号：US20080001586A1

公开(公告)日：2008-01-03

申请号：US10593516

申请日：2005-02-07

申请人： Jochen Kuehner ,  Robert Plikat ,  Stefan Mueller ,  Stephan Rees ,  Armin Ruf

发明人： Jochen Kuehner ,  Robert Plikat ,  Stefan Mueller ,  Stephan Rees ,  Armin Ruf

IPC分类号： G05F1/10

CPC分类号： H03K4/02 ,  H03K17/04123 ,  H03K17/0822 ,  H03K17/166

摘要： A control circuit for controlling an electronic circuit, which has a current path through a semiconductor switch and a line; when the semiconductor switch is switched, the inductance of the line and/or of a component in the current path producing an excess voltage between a first and a second current-carrying terminal of the semiconductor switch; the control circuit having a controllable current source for charging or discharging a charge-controlled gate of the semiconductor switch with the aid of a control current, as well as a control unit; the control unit controlling the current source in such a manner, that in the case of a switching operation, the terminal voltage across the current-carrying terminals of the semiconductor switch does not exceed a predefined setpoint terminal voltage.

摘要翻译： 一种用于控制具有通过半导体开关和线路的电流通路的电子电路的控制电路; 当切换半导体开关时，电流路径中的线路和/或部件的电感在半导体开关的第一和第二载流端子之间产生过电压; 控制电路具有可控电流源，用于借助控制电流对半导体开关的电荷控制栅极进行充电或放电，以及控制单元; 控制单元以这种方式控制电流源，即在切换操作的情况下，半导体开关的通电端子两端的端子电压不超过预定的设定点终端电压。

公开(公告)号：US07042085B2

公开(公告)日：2006-05-09

申请号：US10492269

申请日：2002-09-26

申请人： Kuno Wolf ,  Stephan Ernst ,  Robert Plikat ,  Wolfgang Feiler

发明人： Kuno Wolf ,  Stephan Ernst ,  Robert Plikat ,  Wolfgang Feiler

IPC分类号： H01L23/34

CPC分类号： H01L24/49 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48111 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/48472 ,  H01L2224/49113 ,  H01L2224/4912 ,  H01L2224/73265 ,  H01L2224/83138 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01052 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A method for packaging electronic assemblies and a multiple chip package, at least one power semiconductor chip being applied to a base plate using a first solder, at least one logic chip being applied to the base plate, the logic chip and the base plate being positioned electrically insulated from one another, at least one logic chip being connected to the at least one power semiconductor chip using signal transmission lines, and the electronic assembly including the at least one power semiconductor chip and the at least one logic chip being packaged using a molding compound in order to provide a multiple chip package.

摘要翻译： 一种用于封装电子组件和多芯片封装的方法，使用第一焊料将至少一个功率半导体芯片施加到基板上，至少一个逻辑芯片被施加到基板，逻辑芯片和基板被定位 电绝缘的至少一个逻辑芯片使用信号传输线连接到所述至少一个功率半导体芯片，并且所述电子组件包括所述至少一个功率半导体芯片和所述至少一个逻辑芯片，其使用模制 复合以提供多芯片封装。

公开(公告)号：US06949439B2

公开(公告)日：2005-09-27

申请号：US10450222

申请日：2002-03-26

申请人： Peter Flohrs ,  Robert Plikat ,  Wolfgang Feiler

发明人： Peter Flohrs ,  Robert Plikat ,  Wolfgang Feiler

IPC分类号： H01L21/331 ,  H01L29/739 ,  H01L21/8224

CPC分类号： H01L29/66333 ,  H01L29/7395

摘要： A semiconductor power component and a method for producing a semiconductor power component, in particular a vertical NPT-IGBT for ignition applications with a breakdown voltage of less than approx. 1000 V. The semiconductor power component includes a wafer substrate of a first conductive type including a rear-side emitter region of a second conductive type and a front-side drift region of the first conductive type; a rear-side anode contact which is connected to the emitter region and extends partially to the front-side surface; a front-side MOS control structure; and a front-side cathode contact which is connected to a front-side source region and a body region of the front-side MOS control structure. The thickness of the drift region is much larger than the width of the space charge region at a defined breakdown voltage; and the thickness of the rear-side emitter region is greater than 5 μm.

摘要翻译： 半导体功率部件和半导体功率部件的制造方法，特别是用于点火应用的垂直NPT-IGBT，击穿电压小于约。 半导体功率部件包括第一导电类型的晶片衬底，其包括第二导电类型的后侧发射极区域和第一导电类型的前侧漂移区域; 背面阳极接触件，其连接到发射极区域并部分地延伸到前侧表面; 前端MOS控制结构; 以及连接到前侧MOS控制结构的前侧源极区域和主体区域的前侧阴极接触件。 在限定的击穿电压下，漂移区的厚度远大于空间电荷区的宽度; 后侧发射极区域的厚度大于5μm。

公开(公告)号：US06734520B2

公开(公告)日：2004-05-11

申请号：US09861427

申请日：2001-05-18

申请人： Holger Kapels ,  Dieter Silber ,  Robert Plikat

发明人： Holger Kapels ,  Dieter Silber ,  Robert Plikat

IPC分类号： H01L27095

CPC分类号： H01L29/7811 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/408 ,  H01L29/7802

摘要： A semiconductor component includes a first layer and at least one adjacent semiconductor layer or metallic layer, which forms a rectifying junction with the first layer. Further semiconductor layers and metallic layers are provided for contacting the component. Insulating or semi-insulating structures are introduced into the first layer in a plane parallel to the rectifying junction. These structures are shaped like dishes with their edges bent up towards the rectifying junction. A method of producing such a semiconductor component is also provided.

摘要翻译： 半导体部件包括第一层和与第一层形成整流结的至少一个相邻的半导体层或金属层。 提供了进一步的半导体层和金属层用于使部件接触。 绝缘或半绝缘结构在平行于整流结的平面中引入第一层。 这些结构的形状像碟子一样弯曲，朝向整流结。 还提供了一种制造这种半导体部件的方法。

公开(公告)号：US06661056B1

公开(公告)日：2003-12-09

申请号：US10168243

申请日：2002-09-26

申请人： Robert Plikat ,  Wolfgang Feiler

发明人： Robert Plikat ,  Wolfgang Feiler

IPC分类号： H01L2976

CPC分类号： H01L29/7802 ,  H01L29/0623 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/7803 ,  H01L29/7832

摘要： The present invention relates to a circuit configuration for protecting against polarity reversal of a DMOS transistor. A charge carrier zone (30) is provided, situated in the drift zone (14) of DMOS transistor (10), made up of individual partial charge carrier zones (32) situated at a distance from one another and connected to one another in a conducting manner, the charge carrier zone (30) having an opposite charge carrier doping from that of the drift zone (14), and being able to be acted upon by a potential that is negative with respect to a potential present at a drain terminal (24) of the DMOS transistor (10), so that a short-circuit current is prevented.

摘要翻译： 本发明涉及一种用于防止DMOS晶体管的极性反转的电路配置。提供了一个电荷载体区（30），位于DMOS晶体管（10）的漂移区（14）中，由各个部分电荷载体 区域（32）彼此间隔一定距离并且以导电方式彼此连接，所述电荷载体区域（30）具有与所述漂移区（14）的载流子相反的电荷载流子，并且能够被起作用 通过相对于存在于DMOS晶体管（10）的漏极端子（24）处的电位为负的电位，使得防止短路电流。

公开(公告)号：US06888336B2

公开(公告)日：2005-05-03

申请号：US10483575

申请日：2003-02-06

申请人： Jochen Kuehner ,  Robert Plikat ,  Klaus Rechberger ,  Jochen Ruopp

发明人： Jochen Kuehner ,  Robert Plikat ,  Klaus Rechberger ,  Jochen Ruopp

IPC分类号： H02H7/08 ,  H02H9/04 ,  H02P5/34

CPC分类号： H02H7/0844 ,  H02H9/047

摘要： An inverter for an electric machine is specified that includes a plurality of switching elements, in particular six, which are positioned in a bridge circuit and produce a connection between the electric machine and a battery. The switching elements built into the low-side branch of the inverter are ones that are conductive without a control voltage present, i.e., normally-on switching elements. That ensures that if the supply voltage is absent and the electric machine is rotating the windings of the electric machine are short circuited and no overvoltages are able to occur. In normal operation the inverter is operated like a conventional inverter, by clocked actuation, but with reversed actuation of the control electrodes, i.e., with control voltage for non-conductive time phases and without control voltage in conductive phases.

摘要翻译： 规定了一种用于电机的逆变器，其包括位于桥式电路中的多个开关元件，特别是六个开关元件，并产生电机和电池之间的连接。 内置在逆变器的低侧分支中的开关元件是在没有控制电压的情况下是导通的，即正常开关元件。 这确保了如果不存在电源电压并且电机正在旋转，则电机的绕组短路并且不会发生过电压。 在正常操作中，逆变器的工作方式与传统的逆变器一样，通过时钟驱动，但反向驱动控制电极，即具有用于非导通时间相位的控制电压，而在导电阶段没有控制电压。

公开(公告)号：US20050006758A1

公开(公告)日：2005-01-13

申请号：US10492269

申请日：2002-09-26

申请人： Kuno Wolf ,  Stephan Ernst ,  Robert Plikat ,  Wolfgang Feiler

发明人： Kuno Wolf ,  Stephan Ernst ,  Robert Plikat ,  Wolfgang Feiler

IPC分类号： H01L25/18 ,  H01L21/58 ,  H01L23/495 ,  H01L25/04 ,  H01L23/34

CPC分类号： H01L24/49 ,  H01L23/49562 ,  H01L23/49575 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48111 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48247 ,  H01L2224/48464 ,  H01L2224/48472 ,  H01L2224/49113 ,  H01L2224/4912 ,  H01L2224/73265 ,  H01L2224/83138 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01052 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/07802 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A method for packaging electronic assemblies and a multiple chip package, at least one power semiconductor chip being applied to a base plate using a first solder, at least one logic chip being applied to the base plate, the logic chip and the base plate being positioned electrically insulated from one another, at least one logic chip being connected to the at least one power semiconductor chip using signal transmission lines, and the electronic assembly including the at least one power semiconductor chip and the at least one logic chip being packaged using a molding compound in order to provide a multiple chip package.

摘要翻译： 一种用于封装电子组件和多芯片封装的方法，使用第一焊料将至少一个功率半导体芯片施加到基板上，至少一个逻辑芯片被施加到基板，逻辑芯片和基板被定位 电绝缘的至少一个逻辑芯片使用信号传输线连接到所述至少一个功率半导体芯片，并且所述电子组件包括所述至少一个功率半导体芯片和所述至少一个逻辑芯片，其使用模制 复合以提供多芯片封装。

公开(公告)号：US06784487B2

公开(公告)日：2004-08-31

申请号：US10220084

申请日：2002-08-26

申请人： Robert Plikat

发明人： Robert Plikat

IPC分类号： H01L2976

CPC分类号： H01L29/7806 ,  H01L27/0629 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/7802

摘要： The invention concerns a monolithically integrated semiconductor component, having a first charge carrier region of a first charge carrier doping; at least two second charge carrier regions with opposite charge carrier doping, patterned within the first charge carrier region at a spacing from one another, and third charge carrier regions, with the first charge carrier doping, patterned within the second charge carrier regions, a PN transition being short-circuited between the second charge carrier regions and the third charge carrier regions via a contacting area (source connection), the first charge carrier region being equipped with a contact (drain connection), and the second charge carrier regions being invertable by means of a contacting area in the region between the first charge carrier region and the third charge carrier region; and having at least one Schottky diode connected in parallel with the charge carrier region and the charge carrier region. Provision is made for the first charge carrier region to have a further contacting area, this contacting area being additionally doped near the surface, depending on the doping concentration of the first region, with a further near-surface charge carrier region of higher concentration, so that an ohmic contact is created and is connected to the anode connection of the at least one Schottky diode.

摘要翻译： 本发明涉及具有第一电荷载体掺杂的第一电荷载流子区的单片集成半导体元件; 具有相反电荷载流子掺杂的至少两个第二电荷载体区域，在第一电荷载流子区域内以彼此间隔开的图案化，以及第三电荷载流子区域，其中第一电荷载流子掺杂在第二载流子区域内图案化，PN 经由接触区域（源极连接）在第二电荷载体区域和第三电荷载流子区域之间短路的第一电荷载流子区域被配置有接触（漏极连接），并且第二电荷载流子区域可被第 在第一电荷载体区域和第三电荷载流子区域之间的区域中的接触区域的装置; 并且具有与电荷载流子区域和电荷载流子区域并联连接的至少一个肖特基二极管。 对于第一电荷载体区域进行设置以具有另外的接触区域，该接触区域根据第一区域的掺杂浓度另外掺杂在表面附近，并且具有更高浓度的另外的近表面电荷载体区域，因此 产生欧姆接触并连接到至少一个肖特基二极管的阳极连接。

公开(公告)号：US06777748B1

公开(公告)日：2004-08-17

申请号：US10031526

申请日：2002-05-09

申请人： Robert Plikat ,  Wolfgang Feiler

发明人： Robert Plikat ,  Wolfgang Feiler

IPC分类号： H01L2976

CPC分类号： F02P3/0435 ,  H01L29/7393

摘要： A bidirectional semiconductor component having two symmetrical MOS transistor structures integrated laterally in a substrate and connected antiserially, their drain terminals being connected to one another. A zone having the same type of conductivity as the drain region yet a higher doping than that of the drain region is situated upstream from a pn junction of one of the MOS transistors in a junction area with the drain region.

摘要翻译： 一种具有两个对称的MOS晶体管结构的双向半导体元件，其侧向集成在基板中并且被连接成反向连接，它们的漏极端子彼此连接。 与漏极区相比具有相同类型的导电性的区域具有比漏极区域更高的掺杂的区域位于与漏极区域的结区域中的一个MOS晶体管的pn结的上游。

公开(公告)号：US06495864B1

公开(公告)日：2002-12-17

申请号：US09700357

申请日：2001-01-11

申请人： Dieter Silber ,  Wolfgang Wondrak ,  Robert Plikat

发明人： Dieter Silber ,  Wolfgang Wondrak ,  Robert Plikat

IPC分类号： H01L2974

CPC分类号： H01L29/408 ,  H01L21/7624 ,  H01L29/7394 ,  H01L29/7436 ,  H01L29/861 ,  H01L29/868

摘要： The invention concerns a semiconductor component with at east one lateral region which is provided to accommodate a lateral electric field strength, whereby the semiconductor body within the body and/or in regions proximal to the surface of the semiconductor body at least over regions thereof has a lateral three-dimensional structure which has vertical recesses in the semiconductor body within which there are electrical conductors which are smaller than in the intervening spaces of the semiconductor body between the recesses, as well as a method for making and of using the semiconductor component.

摘要翻译： 本发明涉及一种在东侧横向区域的半导体部件，其被提供以适应横向电场强度，由此半导体本体内和/或接近半导体本体表面的区域至少在其上的区域具有 横向三维结构在半导体主体中具有垂直凹槽，其中存在比半导体本体在凹部之间的间隔小的电导体，以及制造和使用半导体部件的方法。