公开(公告)号：US20200098921A1

公开(公告)日：2020-03-26

申请号：US16143222

申请日：2018-09-26

Applicant: Willy RACHMADY ,  Patrick MORROW ,  Aaron LILAK ,  Rishabh MEHANDRU ,  Cheng-Ying HUANG ,  Gilbert DEWEY ,  Kimin JUN ,  Ryan KEECH ,  Anh PHAN ,  Ehren MANNEBACH

Inventor： Willy RACHMADY ,  Patrick MORROW ,  Aaron LILAK ,  Rishabh MEHANDRU ,  Cheng-Ying HUANG ,  Gilbert DEWEY ,  Kimin JUN ,  Ryan KEECH ,  Anh PHAN ,  Ehren MANNEBACH

IPC: H01L29/78 ,  H01L21/768 ,  H01L29/06 ,  H01L29/66

Abstract: Embodiments include transistor devices and a method of forming the transistor devices. A transistor device includes a first dielectric over a substrate, and vias on a first metal layer, where the first metal layer is on an etch stop layer that is on the first dielectric. The transistor device also includes a second dielectric over the first metal layer, vias, and etch stop layer, where the vias include sidewalls, top surfaces, and bottom surfaces, and stacked transistors on the second dielectric and the top surfaces of the vias, where the sidewalls and top surfaces of the vias are positioned within a footprint of the stacked transistors. The stacked transistors include gate electrodes and first and second transistor layers. The first metal layer includes conductive materials including tungsten or cobalt. The footprint may include a bottom surface of the first transistor layer and a bottom surface of the gate electrodes.

公开(公告)号：US20210202476A1

公开(公告)日：2021-07-01

申请号：US16728983

申请日：2019-12-27

Applicant: Cheng-Ying Huang ,  Gilbert Dewey ,  Ashish Agrawal ,  Kimin Jun ,  Willy Rachmady ,  Zachary Geiger ,  Cory Bomberger ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy ,  Jack Kavalieros

Inventor： Cheng-Ying Huang ,  Gilbert Dewey ,  Ashish Agrawal ,  Kimin Jun ,  Willy Rachmady ,  Zachary Geiger ,  Cory Bomberger ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy ,  Jack Kavalieros

IPC: H01L27/06 ,  H01L21/683 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/04 ,  H01L29/08 ,  H01L27/092

Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include a monocrystalline channel material over a bottom gate stack. The channel material and the gate stack materials may be formed on a donor substrate at any suitable temperature, and subsequently transferred from the donor substrate to a host substrate that includes lower-level circuitry. The upper-level transistor may be patterned from the transferred layers so that the gate electrode includes one or more bonding layers. Source and drain material may be patterned from a source and drain material layer that was transferred from the donor substrate along with the channel material, or source and drain material may be grown at low temperatures from the transferred channel material.

公开(公告)号：US20210407996A1

公开(公告)日：2021-12-30

申请号：US16913333

申请日：2020-06-26

Applicant: Ashish AGRAWAL ,  Brennen MUELLER ,  Jack T. KAVALIEROS ,  Jessica TORRES ,  Kimin JUN ,  Siddharth CHOUKSEY ,  Willy RACHMADY ,  Koustav GANGULY ,  Ryan KEECH ,  Matthew V. METZ ,  Anand S. MURTHY

Inventor： Ashish AGRAWAL ,  Brennen MUELLER ,  Jack T. KAVALIEROS ,  Jessica TORRES ,  Kimin JUN ,  Siddharth CHOUKSEY ,  Willy RACHMADY ,  Koustav GANGULY ,  Ryan KEECH ,  Matthew V. METZ ,  Anand S. MURTHY

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  H01L21/02 ,  H01L21/8238 ,  H01L29/66

Abstract: Gate-all-around integrated circuit structures having strained dual nanowire/nanoribbon channel structures, and methods of fabricating gate-all-around integrated circuit structures having strained dual nanowire/nanoribbon channel structures, are described. For example, an integrated circuit structure includes a first vertical arrangement of nanowires above a substrate. Individual ones of the first vertical arrangement of nanowires are biaxially tensilely strained. The integrated circuit structure also includes a second vertical arrangement of nanowires above the substrate. Individual ones of the second vertical arrangement of nanowires are biaxially compressively strained. The individual ones of the second vertical arrangement of nanowires are laterally staggered with the individual ones of the first vertical arrangement of nanowires.

公开(公告)号：US20210202378A1

公开(公告)日：2021-07-01

申请号：US16728887

申请日：2019-12-27

Applicant: Gilbert Dewey ,  Ryan Keech ,  Cory Bomberger ,  Cheng-Ying Huang ,  Ashish Agrawal ,  Willy Rachmady ,  Anand Murthy

Inventor： Gilbert Dewey ,  Ryan Keech ,  Cory Bomberger ,  Cheng-Ying Huang ,  Ashish Agrawal ,  Willy Rachmady ,  Anand Murthy

IPC: H01L23/522 ,  H01L27/12 ,  H01L21/762 ,  H01L21/768

Abstract: A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.