公开(公告)号：US20210202476A1

公开(公告)日：2021-07-01

申请号：US16728983

申请日：2019-12-27

申请人： Cheng-Ying Huang ,  Gilbert Dewey ,  Ashish Agrawal ,  Kimin Jun ,  Willy Rachmady ,  Zachary Geiger ,  Cory Bomberger ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy ,  Jack Kavalieros

发明人： Cheng-Ying Huang ,  Gilbert Dewey ,  Ashish Agrawal ,  Kimin Jun ,  Willy Rachmady ,  Zachary Geiger ,  Cory Bomberger ,  Ryan Keech ,  Koustav Ganguly ,  Anand Murthy ,  Jack Kavalieros

IPC分类号： H01L27/06 ,  H01L21/683 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/04 ,  H01L29/08 ,  H01L27/092

摘要： A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include a monocrystalline channel material over a bottom gate stack. The channel material and the gate stack materials may be formed on a donor substrate at any suitable temperature, and subsequently transferred from the donor substrate to a host substrate that includes lower-level circuitry. The upper-level transistor may be patterned from the transferred layers so that the gate electrode includes one or more bonding layers. Source and drain material may be patterned from a source and drain material layer that was transferred from the donor substrate along with the channel material, or source and drain material may be grown at low temperatures from the transferred channel material.

公开(公告)号：US20210202378A1

公开(公告)日：2021-07-01

申请号：US16728887

申请日：2019-12-27

申请人： Gilbert Dewey ,  Ryan Keech ,  Cory Bomberger ,  Cheng-Ying Huang ,  Ashish Agrawal ,  Willy Rachmady ,  Anand Murthy

发明人： Gilbert Dewey ,  Ryan Keech ,  Cory Bomberger ,  Cheng-Ying Huang ,  Ashish Agrawal ,  Willy Rachmady ,  Anand Murthy

IPC分类号： H01L23/522 ,  H01L27/12 ,  H01L21/762 ,  H01L21/768

摘要： A device includes a device level having a metallization structure coupled to a semiconductor device and a transistor above the device level. The transistor has a body including a single crystal group III-V or group IV semiconductor material, a source structure on a first portion of the body and a drain structure on a second portion of the body, where the source structure is separate from the drain structure. The transistor further includes a gate structure including a first gate structure portion in a recess in the body and a second gate structure portion between the source structure and the drain structure. A source contact is coupled with the source structure and a drain contact is coupled with the drain structure. The source contact is in contact with the metallization structure in the device level.

公开(公告)号：US20230090092A1

公开(公告)日：2023-03-23

申请号：US17448382

申请日：2021-09-22

申请人： Aaron D. Lilak ,  Orb Acton ,  Cheng-Ying Huang ,  Gilbert Dewey ,  Ehren Mannebach ,  Anh Phan ,  Willy Rachmady ,  Jack T. Kavalieros

发明人： Aaron D. Lilak ,  Orb Acton ,  Cheng-Ying Huang ,  Gilbert Dewey ,  Ehren Mannebach ,  Anh Phan ,  Willy Rachmady ,  Jack T. Kavalieros

IPC分类号： H01L27/12 ,  H01L21/84

摘要： An integrated circuit having a transistor architecture includes a first semiconductor body and a second semiconductor body. The first and second semiconductor bodies are arranged vertically (e.g., stacked configuration) or horizontally (e.g., forksheet configuration) with respect to each other, and separated from one another by insulator material, and each can be configured for planar or non-planar transistor topology. A first gate structure is on the first semiconductor body, and includes a first gate electrode and a first high-k gate dielectric. A second gate structure is on the second semiconductor body, and includes a second gate electrode and a second high-k gate dielectric. In an example, the first gate electrode includes a layer comprising a compound of silicon and one or more metals; the second gate structure may include a silicide workfunction layer, or not. In one example, the first gate electrode is n-type, and the second gate electrode is p-type.

公开(公告)号：US20130270512A1

公开(公告)日：2013-10-17

申请号：US13976411

申请日：2011-12-19

申请人： Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Niloy Mukherjee ,  Jack Kavalieros ,  Willy Rachmady ,  Van Le ,  Benjamin Chu-Kung ,  Matthew Metz ,  Robert Chau

发明人： Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Niloy Mukherjee ,  Jack Kavalieros ,  Willy Rachmady ,  Van Le ,  Benjamin Chu-Kung ,  Matthew Metz ,  Robert Chau

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/845 ,  B82Y10/00 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/20 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

摘要： Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.

公开(公告)号：US20100163927A1

公开(公告)日：2010-07-01

申请号：US12319097

申请日：2008-12-30

申请人： Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kavalieros

发明人： Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kavalieros

IPC分类号： H01L29/778 ,  H01L21/335

CPC分类号： H01L29/155 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/0653 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7831

摘要： Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed.

摘要翻译： 本文通常描述用于提供包括调制掺杂晶体管的三维互补金属氧化物半导体器件的装置和方法的实施例。 可以描述和要求保护其他实施例。

公开(公告)号：US09123567B2

公开(公告)日：2015-09-01

申请号：US13976411

申请日：2011-12-19

申请人： Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Niloy Mukherjee ,  Jack Kavalieros ,  Willy Rachmady ,  Van Le ,  Benjamin Chu-Kung ,  Matthew Metz ,  Robert Chau

发明人： Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Niloy Mukherjee ,  Jack Kavalieros ,  Willy Rachmady ,  Van Le ,  Benjamin Chu-Kung ,  Matthew Metz ,  Robert Chau

IPC分类号： H01L27/092 ,  H01L29/66 ,  H01L29/775 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/423 ,  H01L29/786 ,  H01L27/12 ,  B82Y10/00 ,  H01L29/78

CPC分类号： H01L21/845 ,  B82Y10/00 ,  H01L21/0228 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/30604 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/8258 ,  H01L27/092 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/16 ,  H01L29/20 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66469 ,  H01L29/775 ,  H01L29/785 ,  H01L29/7853 ,  H01L29/78696

摘要： Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.

摘要翻译： 在同一衬底（例如硅）上的非均质材料如III-V族半导体材料和IV族半导体（例如Ge）共同整合的体系结构和技术。 在实施例中，采用具有交替的纳米线和牺牲层的多层非均相半导体材料堆叠以释放纳米线并允许形成完全包围纳米线晶体管的沟道区域的同轴栅极结构。 在实施例中，各个PMOS和NMOS沟道半导体材料与具有交替的Ge / III-V层的覆盖层的起始衬底共同整合。 在实施例中，单个PMOS和单独NMOS器件内的多个堆叠的纳米线的垂直积分能够为给定的布局区域提供显着的驱动电流。

公开(公告)号：US08633471B2

公开(公告)日：2014-01-21

申请号：US13032777

申请日：2011-02-23

申请人： Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kavalieros

发明人： Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kavalieros

IPC分类号： H01L29/12

CPC分类号： H01L29/155 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/0653 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7831

摘要： Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed, which may include a modulation doped heterostructure, wherein the modulation doped heterostructure may comprise an active portion having a first bandgap and a delta doped portion having a second bandgap.

摘要翻译： 本文通常描述用于提供包括调制掺杂晶体管的三维互补金属氧化物半导体器件的装置和方法的实施例。 可以描述和要求保护其他实施例，其可以包括调制掺杂异质结构，其中调制掺杂异质结构可以包括具有第一带隙的有源部分和具有第二带隙的δ掺杂部分。

公开(公告)号：US07915642B2

公开(公告)日：2011-03-29

申请号：US12319097

申请日：2008-12-30

申请人： Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kavalieros

发明人： Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kavalieros

IPC分类号： H01L29/778

CPC分类号： H01L29/155 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/0653 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7831

摘要： Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed.

摘要翻译： 本文通常描述用于提供包括调制掺杂晶体管的三维互补金属氧化物半导体器件的装置和方法的实施例。 可以描述和要求保护其他实施例。

公开(公告)号：US20140175378A1

公开(公告)日：2014-06-26

申请号：US13722746

申请日：2012-12-20

申请人： Niti Goel ,  Niloy Mukherjee ,  Seung Hoon Sung ,  Van Le ,  Matthew Metz ,  Jack Kavalieros ,  RAVI PILLARISETTY ,  Sanaz Gardner ,  SANSAPTAK DASGUPTA ,  Willy Rachmady ,  BENJAMIN CHU-KUNG ,  MARKO RADOSAVLJEVIC ,  Gilbert Dewey ,  Marc French ,  JESSICA KACHIAN ,  SATYARTH SURI ,  Robert Chau

发明人： Niti Goel ,  Niloy Mukherjee ,  Seung Hoon Sung ,  Van Le ,  Matthew Metz ,  Jack Kavalieros ,  RAVI PILLARISETTY ,  Sanaz Gardner ,  SANSAPTAK DASGUPTA ,  Willy Rachmady ,  BENJAMIN CHU-KUNG ,  MARKO RADOSAVLJEVIC ,  Gilbert Dewey ,  Marc French ,  JESSICA KACHIAN ,  SATYARTH SURI ,  Robert Chau

IPC分类号： H01L21/20 ,  H01L21/764

CPC分类号： H01L21/764 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02494 ,  H01L21/02507 ,  H01L21/02532 ,  H01L21/76232

摘要： An embodiment includes depositing a material onto a substrate where the material includes a different lattice constant than the substrate (e.g., III-V or IV epitaxial (EPI) material on a Si substrate). An embodiment includes an EPI layer formed within a trench having walls that narrow as the trench extends upwards. An embodiment includes an EPI layer formed within a trench using multiple growth temperatures. A defect barrier, formed in the EPI layer when the temperature changes, contains defects within the trench and below the defect barrier. The EPI layer above the defect barrier and within the trench is relatively defect free. An embodiment includes an EPI layer annealed within a trench to induce defect annihilation. An embodiment includes an EPI superlattice formed within a trench and covered with a relatively defect free EPI layer (that is still included in the trench). Other embodiments are described herein.

摘要翻译： 实施例包括将材料沉积到衬底上，其中材料包括与衬底（例如Si衬底上的III-V或IV外延（EPI）材料）不同的晶格常数。 一个实施例包括形成在沟槽内的EPI层，其具有随着沟槽向上延伸而变窄的壁。 实施例包括使用多个生长温度在沟槽内形成的EPI层。 当温度变化时，在EPI层中形成的缺陷屏障在沟槽内和缺陷屏障之下包含缺陷。 缺陷屏障之上和沟槽内的EPI层相对无缺陷。 一个实施方案包括在沟槽内退火以引发缺陷湮灭的EPI层。 一个实施例包括形成在沟槽内并覆盖有相对无缺陷的EPI层（仍包含在沟槽中）的EPI超晶格。 本文描述了其它实施例。

公开(公告)号：US20140099759A1

公开(公告)日：2014-04-10

申请号：US14104096

申请日：2013-12-12

申请人： Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kavalieros

发明人： Ravi Pillarisetty ,  Mantu Hudait ,  Marko Radosavljevic ,  Willy Rachmady ,  Gilbert Dewey ,  Jack Kavalieros

IPC分类号： H01L21/8238

CPC分类号： H01L29/155 ,  H01L21/823807 ,  H01L21/823892 ,  H01L29/0653 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66431 ,  H01L29/66462 ,  H01L29/66795 ,  H01L29/7831

摘要： Embodiments of an apparatus and methods for providing three-dimensional complementary metal oxide semiconductor devices comprising modulation doped transistors are generally described herein. Other embodiments may be described and claimed.

摘要翻译： 本文通常描述用于提供包括调制掺杂晶体管的三维互补金属氧化物半导体器件的装置和方法的实施例。 可以描述和要求保护其他实施例。