公开(公告)号：US20220261308A1

公开(公告)日：2022-08-18

申请号：US17733627

申请日：2022-04-29

申请人： Narasimha Lanka ,  Debendra Das Sharma ,  Lakshmipriya Seshan ,  Swadesh Choudhary ,  Zuoguo Wu ,  Gerald Pasdast

发明人： Narasimha Lanka ,  Debendra Das Sharma ,  Lakshmipriya Seshan ,  Swadesh Choudhary ,  Zuoguo Wu ,  Gerald Pasdast

IPC分类号： G06F11/10 ,  G06F11/07 ,  G06F13/40

摘要： Embodiments herein relate to a die of a multi-die package, wherein the die is coupled with another die via a die-to-die (D2D) interconnect link. The die may transmit a data signal to the other die via a data lane of the D2D interconnect link. The die may further transmit, concurrently with the data signal, a valid signal to the other die via a valid lane of the D2D interconnect link. The valid signal may change logical state at least once during the transmission of the data signal. Other embodiments may be described and claimed.

公开(公告)号：US20220222198A1

公开(公告)日：2022-07-14

申请号：US17708367

申请日：2022-03-30

申请人： Narasimha Lanka ,  Swadesh Choudhary ,  Debendra Das Sharma ,  Lakshmipriya Seshan ,  Zuoguo Wu ,  Gerald Pasdast

发明人： Narasimha Lanka ,  Swadesh Choudhary ,  Debendra Das Sharma ,  Lakshmipriya Seshan ,  Zuoguo Wu ,  Gerald Pasdast

IPC分类号： G06F13/42 ,  H01L25/065 ,  H01L23/538 ,  G06F13/40

摘要： In one embodiment, an apparatus includes: a die-to-die adapter to communicate with protocol layer circuitry and physical layer circuitry; and the physical layer circuitry coupled to the die-to-die adapter, where the physical layer circuitry is to receive and output first information to a second die via an interconnect. The physical layer circuitry may include: a first sideband data receiver to couple to a first sideband data lane and a first sideband clock receiver to couple to a first sideband clock lane; and a second sideband data receiver to couple to a second sideband data lane and a second sideband clock receiver to couple to a second sideband clock lane. The physical layer circuitry may assign a functional sideband comprising: one of the first or second sideband data lanes; and one of the first or second sideband clock lanes. Other embodiments are described and claimed.

公开(公告)号：US20220334932A1

公开(公告)日：2022-10-20

申请号：US17855720

申请日：2022-06-30

申请人： Debendra Das Sharma ,  Swadesh Choudhary ,  Sridhar Muthrasanallur ,  Narasimha Lanka ,  Zuoguo Wu ,  Gerald Pasdast ,  Lakshmipriya Seshan

发明人： Debendra Das Sharma ,  Swadesh Choudhary ,  Sridhar Muthrasanallur ,  Narasimha Lanka ,  Zuoguo Wu ,  Gerald Pasdast ,  Lakshmipriya Seshan

IPC分类号： G06F11/20 ,  G06F13/42 ,  G06F13/40 ,  G06F13/16 ,  G06F11/08

摘要： A retimer includes a first port to couple to a die over a first interconnect, where the first interconnect includes a defined set of lanes and utilizes a first communication technology, and the die is located on a first package with the retimer. The retimer further includes a second port to couple to another retimer over a second interconnect, where the second interconnect utilizes a different second communication technology, and the second retimer is located on a different, second package to facilitate a longer reach communication channel.

公开(公告)号：US20220262756A1

公开(公告)日：2022-08-18

申请号：US17733545

申请日：2022-04-29

申请人： Narasimha Lanka ,  Debendra Das Sharma ,  Lakshmipriya Seshan ,  Gerald Pasdast ,  Zuoguo Wu ,  Swadesh Choudhary

发明人： Narasimha Lanka ,  Debendra Das Sharma ,  Lakshmipriya Seshan ,  Gerald Pasdast ,  Zuoguo Wu ,  Swadesh Choudhary

IPC分类号： H01L23/00 ,  H01L25/10 ,  G06F1/04 ,  H01L23/12 ,  H01L23/538

摘要： Embodiments herein relate to action that are to be taken on various lanes of a die-to-die (D2D) interconnect in the event of clock-gating. Specifically, based on identification that a clock-gating event is to occur, physical layer (PHY) logic may direct PHY electrical circuitry to set the state of various of the lanes. In some embodiments, different actions may be taken based on whether the D2D interconnect is terminated or unterminated. Other embodiments may be described and claimed.

公开(公告)号：US20220237138A1

公开(公告)日：2022-07-28

申请号：US17708386

申请日：2022-03-30

申请人： Narasimha Lanka ,  Lakshmipriya Seshan ,  Swadesh Choudhary ,  Debendra Das Sharma ,  Zuoguo Wu ,  Gerald Pasdast

发明人： Narasimha Lanka ,  Lakshmipriya Seshan ,  Swadesh Choudhary ,  Debendra Das Sharma ,  Zuoguo Wu ,  Gerald Pasdast

IPC分类号： G06F13/40 ,  G06F1/10

摘要： In one embodiment, an apparatus includes: a die-to-die adapter to communicate with a protocol layer and physical layer circuitry, and the physical layer circuitry coupled to the die-to-die adapter, where the physical layer circuitry is to receive and output first information to a second die via an interconnect. The physical layer circuitry, after a reset flow for the first die, is to: perform a sideband initialization of a sideband interface of the interconnect to detect that the second die has completed a reset flow for the second die; and after the sideband initialization, perform a mainband initialization of a mainband interface of the interconnect at a lowest speed, and thereafter perform a mainband training of the mainband interface at a negotiated data rate. Other embodiments are described and claimed.

公开(公告)号：US20220342841A1

公开(公告)日：2022-10-27

申请号：US17856050

申请日：2022-07-01

申请人： Swadesh Choudhary ,  Debendra Das Sharma ,  Narasimha Lanka ,  Lakshmipriya Seshan ,  Gerald Pasdast ,  Zuoguo Wu

发明人： Swadesh Choudhary ,  Debendra Das Sharma ,  Narasimha Lanka ,  Lakshmipriya Seshan ,  Gerald Pasdast ,  Zuoguo Wu

IPC分类号： G06F13/42 ,  G06F11/10

摘要： A die-to-die (D2D) adapter couples to a protocol layer block using a first interface to couple to a protocol layer block and couples to a physical layer (PHY) block using a second interface. The D2D adapter is to determine parameters of a D2D link to couple a first die to a second die and select, based on the parameters, a particular one of a plurality of different data formats for use on the D2D link. Protocol layer data is received at the D2D adapter over the first interface from the protocol layer block. The D2D adapter passes the protocol layer data over the second interface to the PHY block based on the particular data format.

公开(公告)号：US20220271912A1

公开(公告)日：2022-08-25

申请号：US17743085

申请日：2022-05-12

申请人： Gerald Pasdast ,  Peipei Wang ,  Lakshmipriya Seshan ,  Juan Zeng ,  Zuoguo Wu ,  Zhiguo Qian ,  Narasimha Lanka ,  Debendra Das Sharma ,  Swadesh Choudhary

发明人： Gerald Pasdast ,  Peipei Wang ,  Lakshmipriya Seshan ,  Juan Zeng ,  Zuoguo Wu ,  Zhiguo Qian ,  Narasimha Lanka ,  Debendra Das Sharma ,  Swadesh Choudhary

IPC分类号： H04L7/00

摘要： Embodiments herein may relate to a die for use in a multi-die package. The die may include clock circuitry that is able to identify a phase of a data signal to be transmitted and a phase of a clock signal to be transmitted on a die-to-die (D2D) link. The clock circuitry may further be configured adjust the phase of the clock signal such that the phase of the clock signal is approximately 90 degrees from the phase of the data signal such that the clock signal and the data signal are received by a receiver die of the D2D link with a 90 degree phase difference. Other embodiments may be described and claimed.

公开(公告)号：US20220393672A1

公开(公告)日：2022-12-08

申请号：US17889892

申请日：2022-08-17

申请人： Jayen Desai ,  Gerald Pasdast ,  Peipei Wang ,  Debendra Das Sharma

发明人： Jayen Desai ,  Gerald Pasdast ,  Peipei Wang ,  Debendra Das Sharma

IPC分类号： H03K5/13 ,  G06F1/12

摘要： Embodiments herein relate to a clock interpolation system. The system may be configured to identify, at a change in logical state of a recovered clock signal, a logical state of a first signal when the first signal is delayed by a delay value. The system may be further configured to identify, at a change in logical state of a second signal, a logical state of the clock signal when the clock signal is delayed by the delay value. Based on the two identifications, the delay value and/or a timing of the clock signal may be adjusted. Other embodiments may be described and/or claimed.

公开(公告)号：US20190041895A1

公开(公告)日：2019-02-07

申请号：US15952169

申请日：2018-04-12

申请人： Yingyu Miao ,  Gerald Pasdast ,  Peipei Wang ,  Mahesh Kumashikar

发明人： Yingyu Miao ,  Gerald Pasdast ,  Peipei Wang ,  Mahesh Kumashikar

IPC分类号： G06F1/10 ,  H03K5/15 ,  H01L23/66 ,  H01L25/065

摘要： A processing device includes a package, a plurality of dies disposed on the package, where each die comprises a clock receiver, and a single common clock source to generate a common clock signal. The processing device also includes a clock distribution circuitry coupled to the single common clock source. The clock distribution circuitry distributes the common clock signal from the single common clock source to each of the plurality of dies individually. The clock distribution circuitry includes a first group of terminated transmission lines. The first group of terminated transmission lines includes a first terminated transmission line, a second terminated transmission line, and a first termination resistor coupled between the first terminated transmission line and the second terminated transmission line. The first terminated transmission line and the second terminated transmission line receive the common clock signal from the single common clock source.

公开(公告)号：US06326802B1

公开(公告)日：2001-12-04

申请号：US09409387

申请日：1999-09-30

申请人： Paul F. Newman ,  Jeff R. Jones ,  Greg Taylor ,  Chee Bow Lim ,  Gerald Pasdast

发明人： Paul F. Newman ,  Jeff R. Jones ,  Greg Taylor ,  Chee Bow Lim ,  Gerald Pasdast

IPC分类号： H03K190185

CPC分类号： H04L25/0278 ,  H03K19/0005

摘要： An impedance matching arrangement, including an adaptive circuit. The adaptive circuit includes a first adaptive portion allowing impedance matching according to a predetermined first weighting scheme, and a second adaptive portion allowing impedance matching according to a predetermined second weighting scheme which differs from the first weighting scheme. The first adaptive portion is operable substantially during initialization times, and the second adaptive portion is operable substantially outside initialization times. The first adaptive portion may have a binary weighting scheme, and the second adaptive portion may have a linear weighting scheme. Finally, the adaptive 1 circuit is provided as a portion of an integrated circuit (IC) die.

摘要翻译： 一种阻抗匹配装置，包括自适应电路。 自适应电路包括允许根据预定的第一加权方案进行阻抗匹配的第一自适应部分和允许根据与第一加权方案不同的预定第二加权方案进行阻抗匹配的第二自适应部分。 第一自适应部分基本上在初始化时间期间可操作，并且第二自适应部分可在大部分的初始化时间之外操作。 第一自适应部分可以具有二进制加权方案，并且第二自适应部分可以具有线性加权方案。 最后，自适应1电路被提供为集成电路（IC）芯片的一部分。