公开(公告)号：US20220261308A1

公开(公告)日：2022-08-18

申请号：US17733627

申请日：2022-04-29

申请人： Narasimha Lanka ,  Debendra Das Sharma ,  Lakshmipriya Seshan ,  Swadesh Choudhary ,  Zuoguo Wu ,  Gerald Pasdast

发明人： Narasimha Lanka ,  Debendra Das Sharma ,  Lakshmipriya Seshan ,  Swadesh Choudhary ,  Zuoguo Wu ,  Gerald Pasdast

IPC分类号： G06F11/10 ,  G06F11/07 ,  G06F13/40

摘要： Embodiments herein relate to a die of a multi-die package, wherein the die is coupled with another die via a die-to-die (D2D) interconnect link. The die may transmit a data signal to the other die via a data lane of the D2D interconnect link. The die may further transmit, concurrently with the data signal, a valid signal to the other die via a valid lane of the D2D interconnect link. The valid signal may change logical state at least once during the transmission of the data signal. Other embodiments may be described and claimed.

公开(公告)号：US20220222198A1

公开(公告)日：2022-07-14

申请号：US17708367

申请日：2022-03-30

申请人： Narasimha Lanka ,  Swadesh Choudhary ,  Debendra Das Sharma ,  Lakshmipriya Seshan ,  Zuoguo Wu ,  Gerald Pasdast

发明人： Narasimha Lanka ,  Swadesh Choudhary ,  Debendra Das Sharma ,  Lakshmipriya Seshan ,  Zuoguo Wu ,  Gerald Pasdast

IPC分类号： G06F13/42 ,  H01L25/065 ,  H01L23/538 ,  G06F13/40

摘要： In one embodiment, an apparatus includes: a die-to-die adapter to communicate with protocol layer circuitry and physical layer circuitry; and the physical layer circuitry coupled to the die-to-die adapter, where the physical layer circuitry is to receive and output first information to a second die via an interconnect. The physical layer circuitry may include: a first sideband data receiver to couple to a first sideband data lane and a first sideband clock receiver to couple to a first sideband clock lane; and a second sideband data receiver to couple to a second sideband data lane and a second sideband clock receiver to couple to a second sideband clock lane. The physical layer circuitry may assign a functional sideband comprising: one of the first or second sideband data lanes; and one of the first or second sideband clock lanes. Other embodiments are described and claimed.

公开(公告)号：US20220334932A1

公开(公告)日：2022-10-20

申请号：US17855720

申请日：2022-06-30

申请人： Debendra Das Sharma ,  Swadesh Choudhary ,  Sridhar Muthrasanallur ,  Narasimha Lanka ,  Zuoguo Wu ,  Gerald Pasdast ,  Lakshmipriya Seshan

发明人： Debendra Das Sharma ,  Swadesh Choudhary ,  Sridhar Muthrasanallur ,  Narasimha Lanka ,  Zuoguo Wu ,  Gerald Pasdast ,  Lakshmipriya Seshan

IPC分类号： G06F11/20 ,  G06F13/42 ,  G06F13/40 ,  G06F13/16 ,  G06F11/08

摘要： A retimer includes a first port to couple to a die over a first interconnect, where the first interconnect includes a defined set of lanes and utilizes a first communication technology, and the die is located on a first package with the retimer. The retimer further includes a second port to couple to another retimer over a second interconnect, where the second interconnect utilizes a different second communication technology, and the second retimer is located on a different, second package to facilitate a longer reach communication channel.

公开(公告)号：US20220262756A1

公开(公告)日：2022-08-18

申请号：US17733545

申请日：2022-04-29

申请人： Narasimha Lanka ,  Debendra Das Sharma ,  Lakshmipriya Seshan ,  Gerald Pasdast ,  Zuoguo Wu ,  Swadesh Choudhary

发明人： Narasimha Lanka ,  Debendra Das Sharma ,  Lakshmipriya Seshan ,  Gerald Pasdast ,  Zuoguo Wu ,  Swadesh Choudhary

IPC分类号： H01L23/00 ,  H01L25/10 ,  G06F1/04 ,  H01L23/12 ,  H01L23/538

摘要： Embodiments herein relate to action that are to be taken on various lanes of a die-to-die (D2D) interconnect in the event of clock-gating. Specifically, based on identification that a clock-gating event is to occur, physical layer (PHY) logic may direct PHY electrical circuitry to set the state of various of the lanes. In some embodiments, different actions may be taken based on whether the D2D interconnect is terminated or unterminated. Other embodiments may be described and claimed.

公开(公告)号：US20220237138A1

公开(公告)日：2022-07-28

申请号：US17708386

申请日：2022-03-30

申请人： Narasimha Lanka ,  Lakshmipriya Seshan ,  Swadesh Choudhary ,  Debendra Das Sharma ,  Zuoguo Wu ,  Gerald Pasdast

发明人： Narasimha Lanka ,  Lakshmipriya Seshan ,  Swadesh Choudhary ,  Debendra Das Sharma ,  Zuoguo Wu ,  Gerald Pasdast

IPC分类号： G06F13/40 ,  G06F1/10

摘要： In one embodiment, an apparatus includes: a die-to-die adapter to communicate with a protocol layer and physical layer circuitry, and the physical layer circuitry coupled to the die-to-die adapter, where the physical layer circuitry is to receive and output first information to a second die via an interconnect. The physical layer circuitry, after a reset flow for the first die, is to: perform a sideband initialization of a sideband interface of the interconnect to detect that the second die has completed a reset flow for the second die; and after the sideband initialization, perform a mainband initialization of a mainband interface of the interconnect at a lowest speed, and thereafter perform a mainband training of the mainband interface at a negotiated data rate. Other embodiments are described and claimed.

公开(公告)号：US20220342841A1

公开(公告)日：2022-10-27

申请号：US17856050

申请日：2022-07-01

申请人： Swadesh Choudhary ,  Debendra Das Sharma ,  Narasimha Lanka ,  Lakshmipriya Seshan ,  Gerald Pasdast ,  Zuoguo Wu

发明人： Swadesh Choudhary ,  Debendra Das Sharma ,  Narasimha Lanka ,  Lakshmipriya Seshan ,  Gerald Pasdast ,  Zuoguo Wu

IPC分类号： G06F13/42 ,  G06F11/10

摘要： A die-to-die (D2D) adapter couples to a protocol layer block using a first interface to couple to a protocol layer block and couples to a physical layer (PHY) block using a second interface. The D2D adapter is to determine parameters of a D2D link to couple a first die to a second die and select, based on the parameters, a particular one of a plurality of different data formats for use on the D2D link. Protocol layer data is received at the D2D adapter over the first interface from the protocol layer block. The D2D adapter passes the protocol layer data over the second interface to the PHY block based on the particular data format.

公开(公告)号：US20220271912A1

公开(公告)日：2022-08-25

申请号：US17743085

申请日：2022-05-12

申请人： Gerald Pasdast ,  Peipei Wang ,  Lakshmipriya Seshan ,  Juan Zeng ,  Zuoguo Wu ,  Zhiguo Qian ,  Narasimha Lanka ,  Debendra Das Sharma ,  Swadesh Choudhary

发明人： Gerald Pasdast ,  Peipei Wang ,  Lakshmipriya Seshan ,  Juan Zeng ,  Zuoguo Wu ,  Zhiguo Qian ,  Narasimha Lanka ,  Debendra Das Sharma ,  Swadesh Choudhary

IPC分类号： H04L7/00

摘要： Embodiments herein may relate to a die for use in a multi-die package. The die may include clock circuitry that is able to identify a phase of a data signal to be transmitted and a phase of a clock signal to be transmitted on a die-to-die (D2D) link. The clock circuitry may further be configured adjust the phase of the clock signal such that the phase of the clock signal is approximately 90 degrees from the phase of the data signal such that the clock signal and the data signal are received by a receiver die of the D2D link with a 90 degree phase difference. Other embodiments may be described and claimed.

公开(公告)号：US20190324523A1

公开(公告)日：2019-10-24

申请号：US16457930

申请日：2019-06-29

申请人： Michelle C. Jen ,  David J. Harriman ,  Zuoguo Wu ,  Debendra Das Sharma ,  Noam Dolev Geldbard

发明人： Michelle C. Jen ,  David J. Harriman ,  Zuoguo Wu ,  Debendra Das Sharma ,  Noam Dolev Geldbard

IPC分类号： G06F1/3234 ,  G06F1/3225 ,  G06F3/06

摘要： A device includes physical layer (PHY) circuitry including a physical coding sublayer, where the PHY circuitry is configured to alternatively support at least two different power control settings. The device further includes an interface to couple the PHY circuitry to a media access control (MAC) layer, where the interface comprises a set of data pins, a set of command pins, a set of status pins, one or more clock pins, and a plurality of power control pins to receive an indication of a particular one of the at least two power control settings. The PHY circuitry is to apply parameters corresponding to the particular control setting during operation based on the indication.

公开(公告)号：US20140093245A1

公开(公告)日：2014-04-03

申请号：US13629945

申请日：2012-09-28

申请人： Inho Kim ,  Zuoguo Wu

发明人： Inho Kim ,  Zuoguo Wu

IPC分类号： H04J14/02

CPC分类号： H04B10/69 ,  H04B10/40 ,  H04B10/801 ,  H04J14/02 ,  H04L7/00 ,  H04L25/14

摘要： Systems and methods may provide for an optical module including an optical demultiplexer to receive a wavelength division multiplexed (WDM) signal from a single receive optical fiber and separate the WDM signal into a plurality of optical signals. Additionally, the optical module may include a receiver conversion unit to convert the plurality of optical signals into a corresponding plurality of electrical signals. In addition, the optical module may include a buffer chip having a single clock and data recovery (CDR) module to recover a clock from a designated signal in the plurality of electrical signals and distribute the recovered clock to a plurality of data lanes corresponding to the plurality of electrical signals.

摘要翻译： 系统和方法可以提供包括光解复用器的光模块，以从单个接收光纤接收波分复用（WDM）信号，并将WDM信号分离成多个光信号。 另外，光学模块可以包括将多个光信号转换为对应的多个电信号的接收机转换单元。 另外，光学模块可以包括具有单个时钟和数据恢复（CDR）模块的缓冲器芯片，以从多个电信号中的指定信号中恢复时钟，并将恢复的时钟分配给多个对应于 多个电信号。

公开(公告)号：US20060215787A1

公开(公告)日：2006-09-28

申请号：US11091227

申请日：2005-03-28

申请人： Zuoguo Wu ,  Feng Chen

发明人： Zuoguo Wu ,  Feng Chen

IPC分类号： H04L27/00

CPC分类号： H04L27/0002 ,  H03F3/45183 ,  H03F3/45968

摘要： According to one embodiment, a system, apparatus, and method for receiving high-speed signals using a receiver with a transconductance amplifier is presented. The apparatus comprises a transconductance amplifier to receive input voltage derived from an input signal, a clocked current comparator to receive output current from the transconductance amplifier, and a storage element to receive a binary value from the clocked current comparator.

摘要翻译： 根据一个实施例，提出了一种使用具有跨导放大器的接收机来接收高速信号的系统，装置和方法。 该装置包括跨导放大器以接收从输入信号导出的输入电压，时钟电流比较器以接收来自跨导放大器的输出电流，以及存储元件以从时钟电流比较器接收二进制值。