公开(公告)号：US6108390A

公开(公告)日：2000-08-22

申请号：US915690

申请日：1997-08-21

申请人： Russell Bell ,  Saf Asghar

发明人： Russell Bell ,  Saf Asghar

IPC分类号： H04L1/00 ,  H04L25/05 ,  H04L25/49 ,  H04L7/00

CPC分类号： H04L25/49 ,  H04L1/0002 ,  H04L1/0025 ,  H04L1/0032 ,  H04L25/05

摘要： A digital communication system includes a receiver and a transmitter in communication with the receiver over a communication link. The transmitter includes a buffer circuit which receives input data signals for transmission and a control signal. The buffer circuit outputs buffered data signals. A symbol encoder circuit receives the buffered data signals and provides the control signal. The symbol encoder circuit outputs data symbols over the communication link. The buffered data signals are supplied to the symbol encoder circuit in accordance with the control signal. The data symbols may be encoded with a number of data bits. The encoding may be done by voltage-level encoding.

摘要翻译： 数字通信系统包括接收机和通过通信链路与接收机通信的发射机。 发射机包括一个缓冲电路，接收用于传输的输入数据信号和一个控制信号。 缓冲电路输出缓冲数据信号。 符号编码器电路接收缓冲的数据信号并提供控制信号。 符号编码器电路通过通信链路输出数据符号。 缓冲的数据信号根据控制信号提供给符号编码器电路。 数据符号可以用多个数据位进行编码。 编码可以通过电压电平编码来完成。

公开(公告)号：US4839842A

公开(公告)日：1989-06-13

申请号：US77268

申请日：1987-07-24

申请人： Hwa-Sheng Pyi ,  Saf Asghar

发明人： Hwa-Sheng Pyi ,  Saf Asghar

IPC分类号： H04L27/26 ,  G06F7/548 ,  G06G7/22 ,  H03B28/00 ,  H04Q1/457

CPC分类号： H04Q1/4575

摘要： Fast methods of tone detection and tone generation disclosed are particularly suitable for implementation in a digital signal processor. Chebyshev polynomials are employed to generate periodic waveforms and to detect such waveforms. In an alternative aspect of the invention, trigonometric formulae are employed to generate periodic waveforms which are representable as the sum of sine and cosine functions. Unlike analog techniques, the digital techniques do not entail long delays in the generation or detection of tones because a fast iterative recalculation is employed at each step. Accumulated error is avoided by restarting the procedure once a predetermined value is exceeded. Independent choice of a quality factor and a confidence level is provided by the digital tone detection technique.

公开(公告)号：US06218931B1

公开(公告)日：2001-04-17

申请号：US09415427

申请日：1999-10-08

申请人： Saf Asghar ,  David Tobias

发明人： Saf Asghar ,  David Tobias

IPC分类号： H04M1104

CPC分类号： H04L12/2838 ,  H04B1/707 ,  H04B3/54 ,  H04B2203/5433 ,  H04L12/2803 ,  H04L12/282 ,  H04L27/02 ,  H04L27/10 ,  H04L27/2071 ,  H04L2012/2843 ,  H04L2012/285

摘要： Described herein is a network interface for coupling residential appliances into a code-division multiple access (CDMA) network. The network is used to convey appliance control signals and appliance status signals. The network interface includes a transmitter and/or a receiver, depending on the communications needs of the residential appliance. A spreading-code generator in the network interface generates a spreading code that identifies the residential appliance. A spreading mixer modulates a narrowband transmit signal with the spreading code, thereby generating a spread-spectrum transmit signal. The wideband transmit signal is then coupled into the physical medium of the network. In one embodiment, the physical medium is a residential wiring grid, and a wiring interface in the transmitter unit couples the spreading mixer with the residential wiring. Spread-spectrum signals received from the wiring grid are despread with an appropriate spreading code to extract the desired signal. Also described herein is a network interface for a wired network. The network interface includes a modulator configured to receive a stream of transmit data and to generate a modulated carrier signal from the data. The modulated carrier is spread by a direct-sequence spreading circuit, using a node-specific spreading code, into a wideband signal. The wideband signal is then coupled onto the wired network.

摘要翻译： 这里描述的是用于将家用电器耦合到码分多址（CDMA）网络中的网络接口。 该网络用于传送设备控制信号和设备状态信号。 根据住宅电器的通信需要，网络接口包括发射机和/或接收机。 网络接口中的扩展码发生器产生识别家用电器的扩展码。 扩展混频器利用扩展码调制窄带发射信号，从而产生扩频发射信号。 宽带发射信号然后被耦合到网络的物理介质中。 在一个实施例中，物理介质是住宅布线网格，并且发射器单元中的布线接口将扩散混合器与住宅布线耦合。 从布线栅格接收的扩频信号用合适的扩展码进行解扩以提取所需信号。 这里还描述了一种用于有线网络的网络接口。 网络接口包括被配置为接收发射数据流并从该数据生成调制载波信号的调制器。 调制载波由直接序列扩展电路使用节点特定的扩展码扩展到宽带信号中。 宽带信号然后耦合到有线网络上。

公开(公告)号：US6008856A

公开(公告)日：1999-12-28

申请号：US915667

申请日：1997-08-21

申请人： Saf Asghar

发明人： Saf Asghar

IPC分类号： H04N7/04

CPC分类号： H04N7/04 ,  H04N21/233 ,  H04N21/2368

摘要： A method of communicating a video image via an audio communication signal includes the steps of identifying, for a given pixel location of the video image, a set of samples within a stored audio signal having a corresponding bit pattern, generating a marker identifying the location of the given pixel in the video image, and multiplexing the stored audio signal and the marker such that the marker appears within the stored audio signal proximate to the set of samples having the corresponding bit pattern. This method can also include the steps of transmitting the multiplexed signal to a destination device, demultiplexing, at the destination device, to recover the marker and the corresponding bit pattern, illuminating a display at the given pixel location according to the corresponding bit pattern, and converting the corresponding bit pattern into an analog audio signal.

摘要翻译： 一种通过音频通信信号传送视频图像的方法包括以下步骤：针对视频图像的给定像素位置识别存储的具有对应位图案的音频信号内的一组样本，生成标识符， 视频图像中的给定像素，并且将所存储的音频信号和标记多路复用，使得标记出现在接近具有相应位模式的采样集合的存储的音频信号内。 该方法还可以包括以下步骤：将目的地设备发送多路复用信号，在目的地设备解复用以恢复标记和对应的位模式，根据相应的位模式照亮给定像素位置处的显示，以及 将相应的位模式转换为模拟音频信号。

公开(公告)号：US6115762A

公开(公告)日：2000-09-05

申请号：US915766

申请日：1997-08-21

申请人： Russell Bell ,  Saf Asghar ,  Yan Zhou

发明人： Russell Bell ,  Saf Asghar ,  Yan Zhou

IPC分类号： H01Q1/22 ,  G06F13/14

CPC分类号： H01Q1/2275 ,  H01Q1/22

摘要： A computing device, such as a laptop personal computer (PC), a desktop PC, or a personal information device (PID), includes an antenna embedded therein for wireless communications. The antenna may be formed on a printed circuit board installed in the computing device. The antenna may include multiple radiating and receiving elements for mitigating multipath effects and/or responding to steering circuitry to form a directed antenna beam.

摘要翻译： 诸如膝上型计算机（PC），台式PC或个人信息设备（PID）的计算设备包括嵌入其中的用于无线通信的天线。 天线可以形成在安装在计算设备中的印刷电路板上。 天线可以包括用于减轻多径效应的多个辐射和接收元件和/或响应于转向电路以形成定向天线波束。

公开(公告)号：US6032247A

公开(公告)日：2000-02-29

申请号：US969865

申请日：1997-11-14

申请人： Saf Asghar ,  Andrew Mills

发明人： Saf Asghar ,  Andrew Mills

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F15/78 ,  G06F15/00

CPC分类号： G06F9/3836 ,  G06F15/7857 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/382 ,  G06F9/3822 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3885

摘要： A CPU or microprocessor which includes a general purpose CPU component, such as an X86 core, and also includes a DSP core. In a first embodiment, the CPU receives general purpose instructions, such as X86 instructions, wherein certain X86 instruction sequences implement DSP functions. The CPU includes a processor mode register which is written with one or more processor mode bits to indicate whether an instruction sequence implements a DSP function. The CPU also includes an intelligent DSP function decoder or preprocessor which examines the processor mode bits and determines if a DSP function is being executed. If a DSP function is being implemented by an instruction sequence, the DSP function decoder converts or maps the opcodes to a DSP macro instruction that is provided to the DSP core. The DSP core executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. If the processor mode bits indicate that X86 instructions in the instruction memory do not implement a DSP-type function, the opcodes are provided to the X86 core as which occurs in current prior art computer systems. In a second embodiment, the CPU receives sequences of instructions comprising X86 instructions and DSP instructions. The processor mode register is written with one or more processor mode bits to indicate whether an instruction sequence comprises X86 or DSP instructions, and the instructions are routed to the X86 core or to the DSP core accordingly.

摘要翻译： 包括通用CPU组件（例如X86内核）的CPU或微处理器，还包括DSP内核。 在第一实施例中，CPU接收诸如X86指令的通用指令，其中某些X86指令序列实现DSP功能。 CPU包括处理器模式寄存器，其被写入一个或多个处理器模式位以指示指令序列是否实现DSP功能。 CPU还包括智能DSP功能解码器或预处理器，它检查处理器模式位，并确定DSP功能是否正在执行。 如果通过指令序列实现DSP功能，则DSP功能解码器将操作码转换或映射到提供给DSP内核的DSP宏指令。 DSP内核执行一个或多个DSP指令以响应于宏指令来实现所需的DSP功能。 如果处理器模式位指示指令存储器中的X86指令不实现DSP类型功能，则将操作码提供给当前现有技术计算机系统中发生的X86内核。 在第二实施例中，CPU接收包括X86指令和DSP指令的指令序列。 处理器模式寄存器用一个或多个处理器模式位写入，以指示指令序列是否包括X86或DSP指令，并将指令相应地路由到X86内核或DSP内核。

公开(公告)号：US6014719A

公开(公告)日：2000-01-11

申请号：US914611

申请日：1997-08-21

申请人： Yan Zhou ,  Saf Asghar

发明人： Yan Zhou ,  Saf Asghar

IPC分类号： H04L5/06 ,  G06F13/42

CPC分类号： H04L5/06

摘要： A modulated bus interconnects each of the plurality of elements on the bus through a filter having a center frequency corresponding to a carrier frequency which modulated by digital information destined for the particular device. Since the device receives an incoming message through a filter, it detects only those messages which have the appropriate filter characteristics. In order to send a message to another device, the first device must apply the appropriate carrier. Thus, multiple transfers between multiple devices can take place simultaneously on a wide-band transmission medium. A controller can be used to dynamically allocate the bus according to an efficient allocation scheme.

摘要翻译： 调制总线通过滤波器互连总线上的多个元件中的每一个元件，该滤波器具有对应于去往特定器件的数字信息调制的载波频率的中心频率。 由于设备通过过滤器接收到传入消息，因此它只检测那些具有适当过滤器特性的消息。 为了向另一个设备发送消息，第一个设备必须应用相应的运营商。 因此，多个设备之间的多个传输可以在宽带传输介质上同时进行。 可以使用控制器来根据有效的分配方案来动态地分配总线。

公开(公告)号：US5784640A

公开(公告)日：1998-07-21

申请号：US618241

申请日：1996-03-18

申请人： Saf Asghar ,  Mark Ireton ,  John G. Bartkowiak

发明人： Saf Asghar ,  Mark Ireton ,  John G. Bartkowiak

IPC分类号： G06F9/318 ,  G06F9/38 ,  G06F9/30 ,  G06F15/163

CPC分类号： G06F9/3017 ,  G06F9/3879 ,  G06F9/3885 ,  H04Q2213/13036 ,  H04Q2213/1305 ,  H04Q2213/13103 ,  H04Q2213/13106 ,  H04Q2213/13107 ,  H04Q2213/13199 ,  H04Q2213/13299 ,  H04Q2213/13389 ,  H04Q2213/13396

摘要： A CPU or microprocessor which includes a general purpose CPU, such as an X86 core, and a DSP. The CPU also includes an intelligent DSP function decoder or preprocessor which examines X8 opcode sequences and determines if a DSP function is being executed. The function preprocessor includes a look-up table which stores instruction sequences which implement DSP functions. Each pattern in the look-up table is compared with an instruction sequence to determine if one of the patterns substantially matches the instruction sequence. If the DSP function preprocessor determines that a DSP function is being executed, the DSP function preprocessor converts the opcodes to a DSP macro instruction that is provided to the DSP. The DSP executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. If the X86 opcodes in the instruction cache or instruction memory do not indicate or are not intended to perform a DSP-type function, the opcodes are provided to the X86 core. Thus, the DSP offloads these mathematical functions from the X86 core, thereby increasing system performance. The DSP operates in parallel with the X86 core, providing further performance benefits. The CPU of the present invention thus implements DSP functions more efficiently than X86 logic while requiring no additional X86 opcodes. The present invention also generates code that operates transparently on an X86 only CPU or a CPU according to the present invention which includes X86 and DSPs. Thus the present invention is backwards compatible with existing software.

摘要翻译： 包括通用CPU（如X86内核）和DSP的CPU或微处理器。 CPU还包括智能DSP功能解码器或预处理器，用于检查X8操作码序列，并确定DSP功能是否正在执行。 功能预处理器包括一个查找表，其存储执行DSP功能的指令序列。 将查找表中的每个模式与指令序列进行比较，以确定其中一个模式是否基本上与指令序列匹配。 如果DSP功能预处理器确定正在执行DSP功能，则DSP功能预处理器将操作码转换为提供给DSP的DSP宏指令。 DSP响应于宏指令，执行一个或多个DSP指令来实现所需的DSP功能。 如果指令高速缓存或指令存储器中的X86操作码未指示或不打算执行DSP类型功能，则将操作码提供给X86内核。 因此，DSP从X86内核中卸载这些数学函数，从而提高系统性能。 DSP与X86内核并行运行，提供进一步的性能优势。 因此，本发明的CPU比X86逻辑更有效地实现DSP功能，而不需要额外的X86操作码。 本发明还生成根据包括X86和DSP的本发明的仅在X86仅CPU或CPU上透明地操作的代码。 因此，本发明与现有软件向后兼容。

公开(公告)号：US5771394A

公开(公告)日：1998-06-23

申请号：US675304

申请日：1996-07-01

申请人： Saf Asghar ,  Brett Stewart

发明人： Saf Asghar ,  Brett Stewart

IPC分类号： G05B19/18 ,  G05B19/19 ,  G05B19/414 ,  G05D3/12 ,  G11B7/085 ,  G11B7/125 ,  G11B11/105 ,  G11B19/00 ,  G11B21/08 ,  G06F15/40

CPC分类号： G11B7/126 ,  G05B19/4148 ,  G11B19/00 ,  G11B21/083 ,  G05B2219/33167 ,  G05B2219/33168 ,  G05B2219/33251 ,  G05B2219/34033 ,  G05B2219/34047 ,  G05B2219/34236 ,  G05B2219/34367 ,  G05B2219/34399 ,  G05B2219/34418 ,  G05B2219/34431 ,  G05B2219/35263 ,  G05B2219/36502 ,  G05B2219/36506 ,  G11B11/10595 ,  G11B7/08529 ,  G11B7/08541

摘要： A servo loop control apparatus having a master microprocessor and at least one autonomous streamlined signal processor is disclosed. The architecture provides a general purpose controller for use in systems where intensive servo signal processing is required and is well suited to applications where multiple servo control loops operate simultaneously. The operation of the streamlined signal processors is autonomous from the master processor so that critical functions can be dedicated to the streamlined signal processors. This eliminates complex interrupt management and tedious real time scheduling constraints, simplifies system design and improves system performance. The architecture provides an integrated mechanism for implementing multiple, concurrent, complex signal processing and embedded control functions, such as complete servo-mechanism management for high performance disk storage systems.

摘要翻译： 公开了一种具有主微处理器和至少一个自主流线型信号处理器的伺服环路控制装置。 该架构提供了一种通用控制器，用于需要强化伺服信号处理的系统，并且非常适合于多个伺服控制回路同时工作的应用。 简化的信号处理器的操作是从主处理器自主的，使得关键功能可以专用于流线型信号处理器。 这消除了复杂的中断管理和繁琐的实时调度约束，简化了系统设计并提高了系统性能。 该架构为实现多种并发，复杂的信号处理和嵌入式控制功能提供了集成的机制，如高性能磁盘存储系统的完整伺服机制管理。

公开(公告)号：US5754878A

公开(公告)日：1998-05-19

申请号：US618242

申请日：1996-03-18

申请人： Saf Asghar ,  Mark Ireton ,  John G. Bartkowiak

发明人： Saf Asghar ,  Mark Ireton ,  John G. Bartkowiak

IPC分类号： G06F9/318 ,  G06F9/38 ,  G06F15/78 ,  G06F9/30 ,  G06F15/163

CPC分类号： G06F9/382 ,  G06F15/7857 ,  G06F9/3017 ,  G06F9/3879 ,  G06F9/3885

摘要： A CPU or microprocessor which includes a general purpose CPU, such as an X86 core, and a DSP. The CPU also includes an intelligent DSP function decoder or preprocessor which examines X86 opcode sequences and determines if a DSP function is being executed. The function preprocessor includes a pattern recognition detector which stores instruction sequences which implement DSP functions. The pattern recognition detector compares each pattern with an instruction sequence and determines if one of the patterns substantially matches the instruction sequence. If the DSP function preprocessor determines that a DSP function is being executed, the preprocessor converts or maps the opcodes to a DSP macro instruction that is provided to the DSP. The DSP executes one or more DSP instructions to implement the desired DSP function in response to the macro instruction. If the X86 opcodes in the instruction cache or instruction memory do not indicate or are not intended to perform a DSP-type function, the opcodes are provided to the X86 core as which occurs in current prior art computer systems. Thus, the DSP offloads these mathematical functions from the X86 core, thereby increasing system performance. The CPU of the present invention thus implements DSP functions more efficiently than X86 logic while requiring no additional X86 opcodes. The present invention also generates code that operates transparently on an X86 only CPU or a CPU according to the present invention which includes X86 and DSPs. Thus the present invention is backwards compatible with existing software.

摘要翻译： 包括通用CPU（如X86内核）和DSP的CPU或微处理器。 CPU还包括智能DSP功能解码器或预处理器，用于检查X86操作码序列，并确定DSP功能是否正在执行。 功能预处理器包括存储执行DSP功能的指令序列的模式识别检测器。 模式识别检测器将每个模式与指令序列进行比较，并确定模式之一是否基本上与指令序列一致。 如果DSP功能预处理器确定正在执行DSP功能，则预处理器将操作码转换或映射到提供给DSP的DSP宏指令。 DSP响应于宏指令，执行一个或多个DSP指令来实现所需的DSP功能。 如果指令高速缓存或指令存储器中的X86操作码不指示或不旨在执行DSP类型功能，则将操作码提供给当前现有技术计算机系统中发生的X86内核。 因此，DSP从X86内核中卸载这些数学函数，从而提高系统性能。 因此，本发明的CPU比X86逻辑更有效地实现DSP功能，而不需要额外的X86操作码。 本发明还生成根据包括X86和DSP的本发明的仅在X86仅CPU或CPU上透明地操作的代码。 因此，本发明与现有软件向后兼容。