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    SYSTEM ON CHIP
    1.
    发明申请
    SYSTEM ON CHIP 有权
    芯片系统

    公开(公告)号：US20160099211A1

    公开(公告)日：2016-04-07

    申请号：US14872774

    申请日：2015-10-01

    Applicant: Sang-Hoon BAEK ,  Sun-Young PARK ,  Sang-Kyu OH ,  Ha-Young KIM ,  Jung-Ho DO ,  Moo-Gyu BAE ,  Seung-Young LEE

    Inventor： Sang-Hoon BAEK ,  Sun-Young PARK ,  Sang-Kyu OH ,  Ha-Young KIM ,  Jung-Ho DO ,  Moo-Gyu BAE ,  Seung-Young LEE

    IPC: H01L23/522 ,  H01L27/088

    CPC classification number: H01L27/088 ,  H01L21/823431 ,  H01L21/823475 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/0886 ,  H01L27/1104

    Abstract: Systems on chips are provided. A system on chip (SoC) includes a first gate line, a second gate line and a third gate line extending in a first direction, a gate isolation region cutting the first gate line, the second gate line and the third gate line and extending in a second direction across the first direction, a first gate contact formed on the second gate line arranged between the first gate line and the third gate line, and electrically connecting the cut second gate line, a second gate contact formed on the first gate line, a third gate contact formed on the third gate line, a first metal line electrically connecting the second gate contact and the third gate contact, and a second metal line electrically connected to the first gate contact.

    Abstract translation: 提供芯片系统。 片上系统（SoC）包括第一栅极线，第二栅极线和沿第一方向延伸的第三栅极线，栅极隔离区域切割第一栅极线，第二栅极线和第三栅极线并且在 在第一方向上的第二方向，形成在第二栅极线上的第一栅极接触，布置在第一栅极线和第三栅极线之间，并且电连接切割的第二栅极线，形成在第一栅极线上的第二栅极接触， 形成在第三栅极线上的第三栅极触点，电连接第二栅极触点和第三栅极触点的第一金属线以及电连接到第一栅极触点的第二金属线。

    METHOD AND SYSTEM FOR DESIGNING SEMICONDUCTOR DEVICE
    2.
    发明申请
    METHOD AND SYSTEM FOR DESIGNING SEMICONDUCTOR DEVICE 有权
    用于设计半导体器件的方法和系统

    公开(公告)号：US20160098508A1

    公开(公告)日：2016-04-07

    申请号：US14845556

    申请日：2015-09-04

    Applicant: Sang-Hoon BAEK ,  Tae-Joong SONG ,  Gi-Young YANG ,  Jeong-Ho DO

    Inventor： Sang-Hoon BAEK ,  Tae-Joong SONG ,  Gi-Young YANG ,  Jeong-Ho DO

    IPC: G06F17/50

    CPC classification number: G06F17/5072 ,  G06F17/5081 ,  H01L29/6681

    Abstract: A method of designing a semiconductor device and system for designing a semiconductor device are provided. The method of designing a semiconductor device includes providing a standard cell layout which includes an active region and a dummy region; determining a first fin pitch between a first active fin and a second active fin in the active region and a second fin pitch between a first dummy fin and a second dummy fin in the dummy region; placing the first and second active fins in the active region and the first and second dummy fins in the dummy region using the first and second fin pitches; and verifying the standard cell layout.

    Abstract translation: 提供一种设计半导体器件的方法和用于设计半导体器件的系统。 设计半导体器件的方法包括提供包括有源区和虚拟区的标准单元布局; 确定所述有源区域中的第一有源鳍片和第二有源鳍片之间的第一鳍片间距和所述虚拟区域中的第一虚拟鳍片和第二虚拟鳍片之间的第二鳍片间距; 使用第一和第二翅片间距将第一和第二活动翅片放置在活动区域​​中，以及使虚拟区域中的第一和第二虚拟翅片放置; 并验证标准单元布局。

    METHOD FOR DESIGNING AND MANUFACTURING AN INTEGRATED CIRCUIT, SYSTEM FOR CARRYING OUT THE METHOD, AND SYSTEM FOR VERIFYING AN INTEGRATED CIRCUIT
    4.
    发明申请
    METHOD FOR DESIGNING AND MANUFACTURING AN INTEGRATED CIRCUIT, SYSTEM FOR CARRYING OUT THE METHOD, AND SYSTEM FOR VERIFYING AN INTEGRATED CIRCUIT 有权
    用于设计和制造集成电路的方法，用于实现该方法的系统和用于验证集成电路的系统

    公开(公告)号：US20150302135A1

    公开(公告)日：2015-10-22

    申请号：US14690227

    申请日：2015-04-17

    Applicant: Chul-Hong PARK ,  Sang-Hoon BAEK ,  Su-Hyeon KIM ,  Kyoung-Yun BAEK ,  Sung-Wook AHN ,  Sang-Kyu OH ,  Seung-Jae JUNG

    Inventor： Chul-Hong PARK ,  Sang-Hoon BAEK ,  Su-Hyeon KIM ,  Kyoung-Yun BAEK ,  Sung-Wook AHN ,  Sang-Kyu OH ,  Seung-Jae JUNG

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5072

    Abstract: A method of manufacturing an integrated circuit, a system for carrying out the method, and a system for verifying an integrated circuit may use a standard cell layout including a first layout region that may violate design rules. The method for designing an integrated circuit may comprise receiving a data file that includes a scaling enhanced circuit layout, and designing a first standard cell layout using design rules and the data file. The designing the first standard cell layout may include designing a first layout region of the first standard cell layout using the data file, and designing a second region of the first standard cell layout using the design rules.

    Abstract translation: 集成电路的制造方法，用于实施该方法的系统以及用于验证集成电路的系统可以使用包括可能违反设计规则的第一布局区域的标准单元布局。 用于设计集成电路的方法可以包括接收包括缩放增强电路布局的数据文件，以及使用设计规则和数据文件来设计第一标准单元布局。 设计第一标准单元布局可以包括使用数据文件设计第一标准单元布局的第一布局区域，以及使用设计规则设计第一标准单元布局的第二区域。

    Integrated circuit and semiconductor device
    7.
    发明授权
    Integrated circuit and semiconductor device 有权
    集成电路和半导体器件

    公开(公告)号：US09583493B2

    公开(公告)日：2017-02-28

    申请号：US15093504

    申请日：2016-04-07

    Applicant: Ha-young Kim ,  Sung-we Cho ,  Tae-joong Song ,  Sang-hoon Baek

    Inventor： Ha-young Kim ,  Sung-we Cho ,  Tae-joong Song ,  Sang-hoon Baek

    IPC: H01L23/52 ,  H01L27/092 ,  H01L23/528 ,  H01L23/522 ,  H01L27/02

    CPC classification number: H01L27/0924 ,  G06F17/5077 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092

    Abstract: An embodiment includes an integrated circuit comprising a standard cell, the standard cell comprising: first and second active regions having different conductivity types and extending in a first direction; first, second, and third conductive lines extending over the first and second active regions in a second direction substantially perpendicular to the first direction, and disposed parallel to each other; and a cutting layer extending in the first direction between the first and second active regions and separating the first conductive line into a first upper conductive line and a first lower conductive line, the second conductive line into a second upper conductive line and a second lower conductive line, and the third conductive line into a third upper conductive line and a third lower conductive line; wherein: the first upper conductive line and the third lower conductive line are electrically connected together; and the second upper conductive line and the second lower conductive line are electrically connected together.

    Abstract translation: 实施例包括包括标准单元的集成电路，该标准单元包括：具有不同导电类型并沿第一方向延伸的第一和第二有源区; 第一，第二和第三导电线在基本上垂直于第一方向的第二方向上在第一和第二有源区上延伸并彼此平行设置; 以及切割层，其在所述第一和第二有源区域之间沿所述第一方向延伸，并且将所述第一导电线分离成第一上导电线和第一下导电线，所述第二导线变为第二上导电线和第二下导电线 线和第三导线插入第三上导电线和第三下导电线; 其中：所述第一上导电线和所述第三下导电线电连接在一起; 并且第二上导线和第二下导电线电连接在一起。

    Semiconductor integrated circuit and method of designing the same
    8.
    发明授权
    Semiconductor integrated circuit and method of designing the same 有权
    半导体集成电路及其设计方法

    公开(公告)号：US08869089B2

    公开(公告)日：2014-10-21

    申请号：US13708066

    申请日：2012-12-07

    Applicant: Sang-hoon Baek ,  Jae-woo Seo

    Inventor： Sang-hoon Baek ,  Jae-woo Seo

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5068

    Abstract: According to example embodiments of inventive concepts, a method of designing a semiconductor integrated circuit includes: creating a marking layer that indicates at least one semiconductor device of a plurality of semiconductor devices that is to be changed in at least one of width, height, and space thereof from an adjacent semiconductor device; and applying the marking layer to a previously created layout to generate a new library of the at least one semiconductor device that is changed in at least one of width, height, and space from an adjacent semiconductor device. The marking layer may be based on a change in characteristics of the at least one semiconductor device of the plurality of semiconductor devices.

    Abstract translation: 根据发明构思的示例性实施例，一种设计半导体集成电路的方法包括：创建标记层，其指示要在宽度，高度和/或宽度中的至少一个中改变的多个半导体器件中的至少一个半导体器件 其相邻半导体器件的空间; 以及将所述标记层应用于先前创建的布局以生成在与相邻半导体器件的宽度，高度和空间中的至少一个中改变的所述至少一个半导体器件的新库。 标记层可以基于多个半导体器件中的至少一个半导体器件的特性变化。

    SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF DESIGNING THE SAME
    9.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT AND METHOD OF DESIGNING THE SAME 有权
    半导体集成电路及其设计方法

    公开(公告)号：US20130263077A1

    公开(公告)日：2013-10-03

    申请号：US13708066

    申请日：2012-12-07

    Applicant: Sang-hoon BAEK ,  Jae-woo SEO

    Inventor： Sang-hoon BAEK ,  Jae-woo SEO

    IPC: G06F17/50

    CPC classification number: G06F17/5081 ,  G06F17/5068

    Abstract: According to example embodiments of inventive concepts, a method of designing a semiconductor integrated circuit includes: creating a marking layer that indicates at least one semiconductor device of a plurality of semiconductor devices that is to be changed in at least one of width, height, and space thereof from an adjacent semiconductor device; and applying the marking layer to a previously created layout to generate a new library of the at least one semiconductor device that is changed in at least one of width, height, and space from an adjacent semiconductor device. The marking layer may be based on a change in characteristics of the at least one semiconductor device of the plurality of semiconductor devices.

    Abstract translation: 根据发明构思的示例性实施例，一种设计半导体集成电路的方法包括：创建标记层，其指示要在宽度，高度和/或宽度中的至少一个中改变的多个半导体器件中的至少一个半导体器件 其相邻半导体器件的空间; 以及将所述标记层应用于先前创建的布局以生成在与相邻半导体器件的宽度，高度和空间中的至少一个中改变的所述至少一个半导体器件的新库。 标记层可以基于多个半导体器件中的至少一个半导体器件的特性变化。

    INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE
    10.
    发明申请
    INTEGRATED CIRCUIT AND SEMICONDUCTOR DEVICE 有权
    集成电路和半导体器件

    公开(公告)号：US20160300839A1

    公开(公告)日：2016-10-13

    申请号：US15093504

    申请日：2016-04-07

    Applicant: Ha-young Kim ,  Sung-we Cho ,  Tae-joong Song ,  Sang-hoon Baek

    Inventor： Ha-young Kim ,  Sung-we Cho ,  Tae-joong Song ,  Sang-hoon Baek

    IPC: H01L27/092 ,  H01L23/522 ,  H01L27/02 ,  H01L23/528

    CPC classification number: H01L27/0924 ,  G06F17/5077 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/092

    Abstract: An embodiment includes an integrated circuit comprising a standard cell, the standard cell comprising: first and second active regions having different conductivity types and extending in a first direction; first, second, and third conductive lines extending over the first and second active regions in a second direction substantially perpendicular to the first direction, and disposed parallel to each other; and a cutting layer extending in the first direction between the first and second active regions and separating the first conductive line into a first upper conductive line and a first lower conductive line, the second conductive line into a second upper conductive line and a second lower conductive line, and the third conductive line into a third upper conductive line and a third lower conductive line; wherein: the first upper conductive line and the third lower conductive line are electrically connected together; and the second upper conductive line and the second lower conductive line are electrically connected together.

    Abstract translation: 实施例包括包括标准单元的集成电路，该标准单元包括：具有不同导电类型并沿第一方向延伸的第一和第二有源区; 第一，第二和第三导电线在基本上垂直于第一方向的第二方向上在第一和第二有源区上延伸并彼此平行设置; 以及切割层，其在所述第一和第二有源区域之间沿所述第一方向延伸，并且将所述第一导电线分离成第一上导电线和第一下导电线，所述第二导线变为第二上导电线和第二下导电线 线和第三导线插入第三上导电线和第三下导电线; 其中：所述第一上导电线和所述第三下导电线电连接在一起; 并且第二上导线和第二下导电线电连接在一起。

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