公开(公告)号：US09564368B2

公开(公告)日：2017-02-07

申请号：US15077351

申请日：2016-03-22

Applicant: Sanghoon Baek ,  Jae-Ho Park ,  Seolun Yang ,  Taejoong Song ,  Sang-Kyu Oh

Inventor： Sanghoon Baek ,  Jae-Ho Park ,  Seolun Yang ,  Taejoong Song ,  Sang-Kyu Oh

IPC: H01L27/088 ,  H01L21/70 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/027 ,  H01L21/762 ,  H01L27/11 ,  H01L27/108 ,  H01L27/02 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/0274 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/7851

Abstract: A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.

Abstract translation: 制造在第一和第二区域之间具有第一区域，第二区域和第三区域的半导体器件的方法包括分别形成从第一和第二区域中的衬底突出的第一和第二预活性图案，形成掩模图案 将衬底上的第三区域曝光，使用掩模图案分别进行蚀刻掩模的第一蚀刻工艺，分别形成第一和第二有源图案，并在衬底上形成栅极结构。

公开(公告)号：US20160204112A1

公开(公告)日：2016-07-14

申请号：US15077351

申请日：2016-03-22

Applicant: SANGHOON BAEK ,  JAE-HO PARK ,  SEOLUN YANG ,  TAEJOONG SONG ,  SANG-KYU OH

Inventor： SANGHOON BAEK ,  JAE-HO PARK ,  SEOLUN YANG ,  TAEJOONG SONG ,  SANG-KYU OH

IPC: H01L27/11 ,  H01L27/02 ,  H01L29/78

CPC classification number: H01L21/823431 ,  H01L21/0274 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/7851

Abstract: A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.

公开(公告)号：US09431383B2

公开(公告)日：2016-08-30

申请号：US14801121

申请日：2015-07-16

Applicant: Sang-hoon Baek ,  Sang-kyu Oh ,  Jung-ho Do ,  Sun-young Park ,  Seung-young Lee ,  Hyo-sig Won

Inventor： Sang-hoon Baek ,  Sang-kyu Oh ,  Jung-ho Do ,  Sun-young Park ,  Seung-young Lee ,  Hyo-sig Won

IPC: H01L21/70 ,  H01L27/02 ,  H01L27/092 ,  H01L29/423 ,  H01L29/78 ,  H01L27/118

CPC classification number: H01L27/11807 ,  H01L27/0207 ,  H01L27/0924 ,  H01L29/42384 ,  H01L29/6681 ,  H01L29/785 ,  H01L2027/11875

Abstract: An integrated circuit (IC) may include at least one cell including a plurality of conductive lines that extend in a first direction and are in parallel to each other in a second direction that is perpendicular to the first direction, first contacts respectively disposed at two sides of at least one conductive line from among the plurality of conductive lines, and a second contact disposed on the at least one conductive line and the first contacts and forming a single node by being electrically connected to the at least one conductive line and the first contacts.

Abstract translation: 集成电路（IC）可以包括至少一个单元，其包括在垂直于第一方向的第二方向上在第一方向上延伸并彼此平行的多条导线，第一触点分别设置在两侧 的至少一条导线，以及设置在所述至少一个导电线上的第二触点，并且所述第一触点通过电连接到所述至少一个导线和所述第一触点而形成单个节点 。

公开(公告)号：US20160056081A1

公开(公告)日：2016-02-25

申请号：US14814601

申请日：2015-07-31

Applicant: SANGHOON BAEK ,  JAE-HO PARK ,  SEOLUN YANG ,  TAEJOONG SONG ,  SANG-KYU OH

Inventor： SANGHOON BAEK ,  JAE-HO PARK ,  SEOLUN YANG ,  TAEJOONG SONG ,  SANG-KYU OH

IPC: H01L21/8234 ,  H01L27/108 ,  H01L21/762 ,  H01L27/11 ,  H01L21/308 ,  H01L21/027

CPC classification number: H01L21/823431 ,  H01L21/0274 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/7851

Abstract: A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.

Abstract translation: 制造在第一和第二区域之间具有第一区域，第二区域和第三区域的半导体器件的方法包括分别形成从第一和第二区域中的衬底突出的第一和第二预活性图案，形成掩模图案 将衬底上的第三区域曝光，使用掩模图案分别进行蚀刻掩模的第一蚀刻工艺，分别形成第一和第二有源图案，并在衬底上形成栅极结构。

公开(公告)号：US20090284028A1

公开(公告)日：2009-11-19

申请号：US12323311

申请日：2008-11-25

Applicant: Sang Kyu OH

Inventor： Sang Kyu OH

IPC: B62D25/12

CPC classification number: E05B85/107 ,  E05B83/16 ,  Y10T292/57

Abstract: A manipulation lever assembly for a trunk lid may include a manipulation lever including a connection portion wherein the connection portion is pivotally coupled to the trunk lid; and an actuation member, one end portion of which is coupled to a first end portion of the manipulation lever and the other end portion of which is coupled to a locking assembly of the trunk lid, wherein when the locking assembly is unlocked, the actuation member activates the manipulation lever, so that a second end of the manipulation lever is extracted outwards from the trunk lid.

Abstract translation: 用于行李箱盖的操作杆组件可以包括操纵杆，其包括连接部分，其中连接部分枢转地联接到行李箱盖; 以及致动构件，其一端部联接到所述操纵杆的第一端部，并且所述致动构件的另一端部联接到所述行李箱盖的锁定组件，其中当所述锁定组件被解锁时，所述致动构件 激活操纵杆，使得操纵杆的第二端从行李箱盖向外抽出。

公开(公告)号：US20150302135A1

公开(公告)日：2015-10-22

申请号：US14690227

申请日：2015-04-17

Applicant: Chul-Hong PARK ,  Sang-Hoon BAEK ,  Su-Hyeon KIM ,  Kyoung-Yun BAEK ,  Sung-Wook AHN ,  Sang-Kyu OH ,  Seung-Jae JUNG

Inventor： Chul-Hong PARK ,  Sang-Hoon BAEK ,  Su-Hyeon KIM ,  Kyoung-Yun BAEK ,  Sung-Wook AHN ,  Sang-Kyu OH ,  Seung-Jae JUNG

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5072

Abstract: A method of manufacturing an integrated circuit, a system for carrying out the method, and a system for verifying an integrated circuit may use a standard cell layout including a first layout region that may violate design rules. The method for designing an integrated circuit may comprise receiving a data file that includes a scaling enhanced circuit layout, and designing a first standard cell layout using design rules and the data file. The designing the first standard cell layout may include designing a first layout region of the first standard cell layout using the data file, and designing a second region of the first standard cell layout using the design rules.

Abstract translation: 集成电路的制造方法，用于实施该方法的系统以及用于验证集成电路的系统可以使用包括可能违反设计规则的第一布局区域的标准单元布局。 用于设计集成电路的方法可以包括接收包括缩放增强电路布局的数据文件，以及使用设计规则和数据文件来设计第一标准单元布局。 设计第一标准单元布局可以包括使用数据文件设计第一标准单元布局的第一布局区域，以及使用设计规则设计第一标准单元布局的第二区域。

公开(公告)号：US20150137252A1

公开(公告)日：2015-05-21

申请号：US14474484

申请日：2014-09-02

Applicant: Sang-Hoon Baek ,  Sang-Kyu Oh ,  Na-Ya Ha ,  Seung-Weon Paek ,  Tae-Joong Song

Inventor： Sang-Hoon Baek ,  Sang-Kyu Oh ,  Na-Ya Ha ,  Seung-Weon Paek ,  Tae-Joong Song

IPC: G06F17/50 ,  H01L27/11 ,  H01L27/115 ,  H01L27/108

CPC classification number: G06F17/5072 ,  G06F17/5068 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/1104 ,  H01L29/6681

Abstract: A layout design system includes a processor; a storage unit configured to store a first unit design having a first area, wherein in the first unit design, a termination is not placed on a border thereof; and a design module configured to generate a second unit design having a second area larger than the first area by placing the termination on a border of the first unit.

Abstract translation: 布局设计系统包括处理器; 存储单元，其被配置为存储具有第一区域的第一单元设计，其中在所述第一单元设计中，终端不被放置在其边界上; 以及设计模块，其被配置为通过将所述终端放置在所述第一单元的边界上来生成具有大于所述第一区域的第二区域的第二单元设计。

公开(公告)号：US09324619B2

公开(公告)日：2016-04-26

申请号：US14814601

申请日：2015-07-31

Applicant: Sanghoon Baek ,  Jae-Ho Park ,  Seolun Yang ,  Taejoong Song ,  Sang-Kyu Oh

Inventor： Sanghoon Baek ,  Jae-Ho Park ,  Seolun Yang ,  Taejoong Song ,  Sang-Kyu Oh

IPC: H01L21/33 ,  H01L21/82 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/027 ,  H01L21/762 ,  H01L27/11 ,  H01L27/108

CPC classification number: H01L21/823431 ,  H01L21/0274 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/10879 ,  H01L27/10894 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/7851

Abstract: A method of fabricating a semiconductor device having a first region, a second region, and a third region between the first and second regions includes forming first and second preliminary active patterns protruding from a substrate in the first and second regions, respectively, forming mask patterns exposing the third region on the substrate, performing a first etching process using the mask patterns an etch mask to form first and second active patterns, respectively, and forming gate structures on the substrate.

Abstract translation: 制造在第一和第二区域之间具有第一区域，第二区域和第三区域的半导体器件的方法包括分别形成从第一和第二区域中的衬底突出的第一和第二预活性图案，形成掩模图案 将衬底上的第三区域曝光，使用掩模图案分别进行蚀刻掩模的第一蚀刻工艺，分别形成第一和第二有源图案，并在衬底上形成栅极结构。

公开(公告)号：US20160026749A1

公开(公告)日：2016-01-28

申请号：US14709885

申请日：2015-05-12

Applicant: TAEJOONG SONG ,  JAE-HO PARK ,  SANGHOON BAEK ,  GIYOUNG YANG ,  SANG-KYU OH ,  HYOSIG WON

Inventor： TAEJOONG SONG ,  JAE-HO PARK ,  SANGHOON BAEK ,  GIYOUNG YANG ,  SANG-KYU OH ,  HYOSIG WON

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5072 ,  G06F2217/84

Abstract: A method of generating a photo mask for use during fabrication of a semiconductor device includes; generating an initial layout design including critical circuit paths and non-critical circuit paths by shielding all gate line patterns used to implement transistors in the critical circuits and non-critical circuits, and thereafter generating a layout design from the initial layout design by selectively un-shielding a non-critical gate line pattern among the gate line patterns used to implement a gate of a non-critical transistor in a non-critical circuit, while retaining the shielding of all critical gate line patterns among the gate line patterns.

Abstract translation: 一种在制造半导体器件期间产生光掩模的方法包括： 通过屏蔽用于在关键电路和非关键电路中实现晶体管的所有栅极线图案，产生包括关键电路路径和非关键电路路径的初始布局设计，然后通过选择性地取消初始布局设计，从初始布局设计生成布局设计， 在用于在非关键电路中实现非关键晶体管的栅极的栅极线图案之间屏蔽非关键栅极线图案，同时保持栅极线图案之间的所有关键栅极线图案的屏蔽。

公开(公告)号：US09652580B2

公开(公告)日：2017-05-16

申请号：US14709885

申请日：2015-05-12

Applicant: Taejoong Song ,  Jae-Ho Park ,  Sanghoon Baek ,  Giyoung Yang ,  Sang-Kyu Oh ,  Hyosig Won

Inventor： Taejoong Song ,  Jae-Ho Park ,  Sanghoon Baek ,  Giyoung Yang ,  Sang-Kyu Oh ,  Hyosig Won

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5072 ,  G06F2217/84

Abstract: A method of generating a photo mask for use during fabrication of a semiconductor device includes; generating an initial layout design including critical circuit paths and non-critical circuit paths by shielding all gate line patterns used to implement transistors in the critical circuits and non-critical circuits, and thereafter generating a layout design from the initial layout design by selectively un-shielding a non-critical gate line pattern among the gate line patterns used to implement a gate of a non-critical transistor in a non-critical circuit, while retaining the shielding of all critical gate line patterns among the gate line patterns.