公开(公告)号：US20100211765A1

公开(公告)日：2010-08-19

申请号：US12770576

申请日：2010-04-29

申请人： Mike H. Amidi ,  Satyadev Kolli

发明人： Mike H. Amidi ,  Satyadev Kolli

IPC分类号： G06F1/24 ,  G11C5/14

CPC分类号： G11C5/143 ,  G11C7/22 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2211/4067

摘要： A system, method and apparatus for clock and power fault detection for a memory module is provided. In one embodiment, a system is provided. The system includes a voltage detection circuit and a clock detection circuit. The system further includes a controller coupled to the voltage detection circuit and the clock detection circuit. The system also includes a memory control state machine coupled to the controller. The system includes volatile memory coupled to the memory control state machine. The system further includes a battery and battery regulation circuitry coupled to the controller and the memory control state machine. The battery, battery regulation circuitry, volatile memory, memory control state machine, controller, clock detection circuit and voltage detection circuit are all collectively included in a unitary memory module.

公开(公告)号：US20080123305A1

公开(公告)日：2008-05-29

申请号：US11605809

申请日：2006-11-28

申请人： Hossein Amidi ,  Satyadev Kolli

发明人： Hossein Amidi ,  Satyadev Kolli

IPC分类号： H05K1/14

CPC分类号： H05K1/181 ,  G11C5/02 ,  G11C5/04 ,  G11C8/16 ,  H05K1/117 ,  H05K2201/09972 ,  H05K2201/10159 ,  Y02P70/611

摘要： A dual-channel memory module for use in computing devices is disclosed. The memory module can include a substrate having a base portion, a first connector portion, and a second connector portion spaced apart and electrically insulated from the first connector portion. A first set of memory devices is disposed on the base portion and in electrical communication with the first connector portion, and a second set of memory devices is disposed on the base portion and in electrical communication with the second connector portion. The first and second sets of memory devices are independent of each other.

摘要翻译： 公开了一种用于计算设备的双通道内存模块。 存储器模块可以包括具有基座部分，第一连接器部分和与第一连接器部分间隔开并与之电绝缘的第二连接器部分的基板。 第一组存储器件设置在基座部分上并且与第一连接器部分电连通，并且第二组存储器件设置在基座部分上并与第二连接器部分电连通。 第一组和第二组存储器件彼此独立。

公开(公告)号：US20130036264A1

公开(公告)日：2013-02-07

申请号：US13568694

申请日：2012-08-07

申请人： Hossein Amidi ,  Kelvin A. Marino ,  Satyadev Kolli

发明人： Hossein Amidi ,  Kelvin A. Marino ,  Satyadev Kolli

IPC分类号： G06F12/00

CPC分类号： G11C8/12 ,  G11C5/04 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222

摘要： A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a second memory rank. An emulator coupled to the memory module activates and controls one individual memory rank from either the first memory rank, the second memory rank, the third memory rank, or the fourth memory rank based on the signals received from a memory controller.

摘要翻译： 透明的四级存储器模块具有前侧和后侧。 前侧具有堆叠在第一存储器等级上的第三存储器级。 背面具有堆叠在第二存储器等级上的第四存储器级。 耦合到存储器模块的仿真器基于从存储器控制器接收的信号来激活并控制来自第一存储器级，第二存储器级，第三存储器级或第四存储器级的一个单独的存储器级。

公开(公告)号：US08068378B2

公开(公告)日：2011-11-29

申请号：US12770610

申请日：2010-04-29

申请人： Mike H. Amidi ,  Satyadev Kolli

发明人： Mike H. Amidi ,  Satyadev Kolli

IPC分类号： G11C5/14

CPC分类号： G11C5/143 ,  G11C7/22 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2211/4067

摘要： A system, method and apparatus for clock and power fault detection for a memory module is provided. In one embodiment, a system is provided. The system includes a voltage detection circuit and a clock detection circuit. The system further includes a controller coupled to the voltage detection circuit and the clock detection circuit. The system also includes a memory control state machine coupled to the controller. The system includes volatile memory coupled to the memory control state machine. The system further includes a battery and battery regulation circuitry coupled to the controller and the memory control state machine. The battery, battery regulation circuitry, volatile memory, memory control state machine, controller, clock detection circuit and voltage detection circuit are all collectively included in a unitary memory module.

摘要翻译： 提供了一种用于存储器模块的时钟和电源故障检测的系统，方法和装置。 在一个实施例中，提供了一种系统。 该系统包括电压检测电路和时钟检测电路。 该系统还包括耦合到电压检测电路和时钟检测电路的控制器。 该系统还包括耦合到控制器的存储器控​​制状态机。 该系统包括耦合到存储器控制状态机的易失性存储器。 该系统还包括耦合到控制器和存储器控制状态机的电池和电池调节电路。 电池，电池调节电路，易失性存储器，存储器控制状态机，控制器，时钟检测电路和电压检测电路都集成在一体的存储器模块中。

公开(公告)号：US20100238754A1

公开(公告)日：2010-09-23

申请号：US12770610

申请日：2010-04-29

申请人： Mike H. Amidi ,  Satyadev Kolli

发明人： Mike H. Amidi ,  Satyadev Kolli

IPC分类号： G11C5/14

CPC分类号： G11C5/143 ,  G11C7/22 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2211/4067

摘要： A system, method and apparatus for clock and power fault detection for a memory module is provided. In one embodiment, a system is provided. The system includes a voltage detection circuit and a clock detection circuit. The system further includes a controller coupled to the voltage detection circuit and the clock detection circuit. The system also includes a memory control state machine coupled to the controller. The system includes volatile memory coupled to the memory control state machine. The system further includes a battery and battery regulation circuitry coupled to the controller and the memory control state machine. The battery, battery regulation circuitry, volatile memory, memory control state machine, controller, clock detection circuit and voltage detection circuit are all collectively included in a unitary memory module.

摘要翻译： 提供了一种用于存储器模块的时钟和电源故障检测的系统，方法和装置。 在一个实施例中，提供了一种系统。 该系统包括电压检测电路和时钟检测电路。 该系统还包括耦合到电压检测电路和时钟检测电路的控制器。 该系统还包括耦合到控制器的存储器控​​制状态机。 该系统包括耦合到存储器控制状态机的易失性存储器。 该系统还包括耦合到控制器和存储器控制状态机的电池和电池调节电路。 电池，电池调节电路，易失性存储器，存储器控制状态机，控制器，时钟检测电路和电压检测电路都集成在一体的存储器模块中。

公开(公告)号：US08990489B2

公开(公告)日：2015-03-24

申请号：US13568694

申请日：2012-08-07

申请人： Hossein Amidi ,  Kelvin A. Marino ,  Satyadev Kolli

发明人： Hossein Amidi ,  Kelvin A. Marino ,  Satyadev Kolli

IPC分类号： G06F12/00 ,  G11C8/00 ,  G11C8/12 ,  G11C5/04 ,  G11C7/10 ,  G11C7/22

CPC分类号： G11C8/12 ,  G11C5/04 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222

摘要： A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a second memory rank. An emulator coupled to the memory module activates and controls one individual memory rank from either the first memory rank, the second memory rank, the third memory rank, or the fourth memory rank based on the signals received from a memory controller.

摘要翻译： 透明的四级存储器模块具有前侧和后侧。 前侧具有堆叠在第一存储器等级上的第三存储器级。 背面具有堆叠在第二存储器等级上的第四存储器级。 耦合到存储器模块的仿真器基于从存储器控制器接收的信号来激活并控制来自第一存储器级，第二存储器级，第三存储器级或第四存储器级的一个单独的存储器级。

公开(公告)号：US08644105B2

公开(公告)日：2014-02-04

申请号：US12770576

申请日：2010-04-29

申请人： Mike H. Amidi ,  Satyadev Kolli

发明人： Mike H. Amidi ,  Satyadev Kolli

IPC分类号： G11C8/00

CPC分类号： G11C5/143 ,  G11C7/22 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4074 ,  G11C11/4076 ,  G11C2211/4067

摘要： A system, method and apparatus for clock and power fault detection for a memory module is provided. In one embodiment, a system is provided. The system includes a voltage detection circuit and a clock detection circuit. The system further includes a controller coupled to the voltage detection circuit and the clock detection circuit. The system also includes a memory control state machine coupled to the controller. The system includes volatile memory coupled to the memory control state machine. The system further includes a battery and battery regulation circuitry coupled to the controller and the memory control state machine. The battery, battery regulation circuitry, volatile memory, memory control state machine, controller, clock detection circuit and voltage detection circuit are all collectively included in a unitary memory module.

摘要翻译： 提供了一种用于存储器模块的时钟和电源故障检测的系统，方法和装置。 在一个实施例中，提供了一种系统。 该系统包括电压检测电路和时钟检测电路。 该系统还包括耦合到电压检测电路和时钟检测电路的控制器。 该系统还包括耦合到控制器的存储器控​​制状态机。 该系统包括耦合到存储器控制状态机的易失性存储器。 该系统还包括耦合到控制器和存储器控制状态机的电池和电池调节电路。 电池，电池调节电路，易失性存储器，存储器控制状态机，控制器，时钟检测电路和电压检测电路都集成在一体式存储器模块中。

公开(公告)号：US20110125966A1

公开(公告)日：2011-05-26

申请号：US12902073

申请日：2010-10-11

申请人： Hossein Amidi ,  Kelvin A. Marino ,  Satyadev Kolli

发明人： Hossein Amidi ,  Kelvin A. Marino ,  Satyadev Kolli

IPC分类号： G06F12/00

CPC分类号： G11C8/12 ,  G11C5/04 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222

摘要： A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a second memory rank. An emulator coupled to the memory module activates and controls one individual memory rank from either the first memory rank, the second memory rank, the third memory rank, or the fourth memory rank based on the signals received from a memory controller.

摘要翻译： 透明的四级存储器模块具有前侧和后侧。 前侧具有堆叠在第一存储器等级上的第三存储器级。 背面具有堆叠在第二存储器等级上的第四存储器级。 耦合到存储器模块的仿真器基于从存储器控制器接收的信号来激活并控制来自第一存储器级，第二存储器级，第三存储器级或第四存储器级的一个单独的存储器级。

公开(公告)号：US20080002447A1

公开(公告)日：2008-01-03

申请号：US11478971

申请日：2006-06-29

申请人： Alan Michael Gulachenski ,  Satyadev Kolli ,  Jan Hendrik Helbers

发明人： Alan Michael Gulachenski ,  Satyadev Kolli ,  Jan Hendrik Helbers

IPC分类号： G11C5/02

CPC分类号： G11C5/04 ,  H05K1/181 ,  H05K2201/09409 ,  H05K2203/1572 ,  Y02P70/611

摘要： A memory supermodule containing two or more memory modules disposed on a common circuit board. Also, a memory supermodule comprising two or more memory modules, each module comprising a circuit board, the circuit boards connected by a flexible circuit. All modules in a supermodule share a single set of contact pads for establishing signal connection with a system in which the supermodule is used.

摘要翻译： 一个包含两个或多个存储器模块的存储器超模，该存储器模块设置在公共电路板上。 而且，包括两个或多个存储器模块的存储器超模块，每个模块包括电路板，电路板由柔性电路连接。 超模中的所有模块共享一组接触垫，用于与使用超模的系统建立信号连接。

公开(公告)号：US10755757B2

公开(公告)日：2020-08-25

申请号：US12902073

申请日：2010-10-11

申请人： Hossein Amidi ,  Kelvin A. Marino ,  Satyadev Kolli

发明人： Hossein Amidi ,  Kelvin A. Marino ,  Satyadev Kolli

IPC分类号： G11C8/12 ,  G11C5/04 ,  G11C7/10 ,  G11C7/22

摘要： A transparent four rank memory module has a front side and a back side. The front side has a third memory rank stacked on a first memory rank. The back side has a fourth memory rank stacked on a second memory rank. An emulator coupled to the memory module activates and controls one individual memory rank from either the first memory rank, the second memory rank, the third memory rank, or the fourth memory rank based on the signals received from a memory controller.