公开(公告)号：US20060023542A1

公开(公告)日：2006-02-02

申请号：US10900246

申请日：2004-07-27

申请人： Scott Derner ,  Venkatraghavan Bringivijayaraghavan ,  Abhay Dixit ,  Scot Graham ,  Stephen Porter ,  Ethan Williford

发明人： Scott Derner ,  Venkatraghavan Bringivijayaraghavan ,  Abhay Dixit ,  Scot Graham ,  Stephen Porter ,  Ethan Williford

IPC分类号： G11C7/00

CPC分类号： G11C11/412 ,  G11C11/4085

摘要： Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus are provided to determine whether any of the word lines in a section of a memory array are active. If any one of the plurality of word lines is active, each of the inactive word lines in the section are coupled to a negative voltage level. If none of the plurality of word lines is active, each of the plurality of word lines is coupled to ground to reduce GIDL.

摘要翻译： 利用负字线架构降低存储器件漏极漏极泄漏（GIDL）的技术。 更具体地，提供了一种方法和装置，用于确定存储器阵列的一部分中的任何字线是否是活动的。 如果多个字线中的任一个是活动的，则该部分中的每个非活动字线被耦合到负电压电平。 如果多个字线中没有一个是有效的，则多个字线中的每个字线被耦合到地来减少GIDL。

公开(公告)号：US20060139988A1

公开(公告)日：2006-06-29

申请号：US11358234

申请日：2006-02-21

申请人： Luan Tran ,  Stephen Porter ,  Scot Graham ,  Steven Howell

发明人： Luan Tran ,  Stephen Porter ,  Scot Graham ,  Steven Howell

IPC分类号： G11C11/24 ,  G11C11/401

CPC分类号： G11C7/02 ,  G11C7/12 ,  G11C7/18 ,  G11C11/401 ,  G11C11/4097 ,  G11C29/816 ,  G11C2207/002 ,  G11C2207/005 ,  Y10S257/906

摘要： A memory device includes isolation devices located between-memory cells. A plurality of isolation lines connects the isolation devices to a positive voltage during normal operations but still keeps the isolation devices in the off state to provide isolation between the memory cells. A current control circuit is placed between the isolation lines and a power node for reducing a current flowing between the isolation lines and the power node in case a deflect occurs at any one of isolation devices.

摘要翻译： 存储器件包括位于存储器单元之间的隔离器件。 多个隔离线在正常操作期间将隔离装置连接到正电压，但是仍然使隔离装置保持在关闭状态以提供存储单元之间的隔离。 在隔离线路和电源节点之间放置电流控制电路，用于在任何一个隔离装置发生偏转的情况下减少在隔离线路与功率节点之间流动的电流。

公开(公告)号：US20070263470A1

公开(公告)日：2007-11-15

申请号：US11879396

申请日：2007-07-17

申请人： Scott Derner ,  Venkatraghavan Bringivijayaraghavan ,  Abhay Dixit ,  Scot Graham ,  Stephen Porter ,  Ethan Williford

发明人： Scott Derner ,  Venkatraghavan Bringivijayaraghavan ,  Abhay Dixit ,  Scot Graham ,  Stephen Porter ,  Ethan Williford

IPC分类号： G11C5/14

CPC分类号： G11C11/412 ,  G11C11/4085

摘要： Techniques for reducing gate induced drain leakage (GIDL) in memory devices utilizing negative wordline architectures. More specifically, a method and apparatus are provided to determine whether any of the word lines in a section of a memory array are active. If any one of the plurality of word lines is active, each of the inactive word lines in the section are coupled to a negative voltage level. If none of the plurality of word lines is active, each of the plurality of word lines is coupled to ground to reduce GIDL.

公开(公告)号：US20060256630A1

公开(公告)日：2006-11-16

申请号：US11489119

申请日：2006-07-19

申请人： Scott Derner ,  Stephen Porter ,  Scot Graham ,  Ethan Williford ,  Kevin Duesman

发明人： Scott Derner ,  Stephen Porter ,  Scot Graham ,  Ethan Williford ,  Kevin Duesman

IPC分类号： G11C29/00

CPC分类号： G11C7/12 ,  G11C7/02 ,  G11C7/1048 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4096 ,  G11C2207/002

摘要： A method and apparatus is provided for reducing the current in a memory device. Peripheral device control signals are translated to the wordline off voltage level, such as a negative wordline voltage. The translated signals prevent the peripheral devices from conducting current in the wordline off mode, even if a wordline-to-digitline short should occur. The control signals may include a column select signal for a column select device and an active pull-up signal for a sense amplifier, among others. Additionally, an equalization circuit having high and low resistance components is provided for the memory device. The equalization circuit limits current, even if a wordline-to-digitline short occurs.

公开(公告)号：US20060023493A1

公开(公告)日：2006-02-02

申请号：US10902728

申请日：2004-07-29

申请人： Scott Derner ,  Stephen Porter ,  Scot Graham ,  Ethan Williford ,  Kevin Duesman

发明人： Scott Derner ,  Stephen Porter ,  Scot Graham ,  Ethan Williford ,  Kevin Duesman

IPC分类号： G11C11/00

CPC分类号： G11C7/12 ,  G11C7/02 ,  G11C7/1048 ,  G11C11/4085 ,  G11C11/4094 ,  G11C11/4096 ,  G11C2207/002

摘要： A method and apparatus is provided for reducing the current in a memory device. Peripheral device control signals are translated to the wordline off voltage level, such as a negative wordline voltage. The translated signals prevent the peripheral devices from conducting current in the wordline off mode, even if a wordline-to-digitline short should occur. The control signals may include a column select signal for a column select device and an active pull-up signal for a sense amplifier, among others. Additionally, an equalization circuit having high and low resistance components is provided for the memory device. The equalization circuit limits current, even if a wordline-to-digitline short occurs.

摘要翻译： 提供了一种减少存储器件中的电流的方法和装置。 外围设备控制信号被转换为字线关断电压电平，例如负字线电压。 转换后的信号可防止外围设备在字线关闭模式下传导电流，即使发生字线数字短路。 控制信号可以包括列选择装置的列选择信号和用于感测放大器的有源上拉信号等。 此外，为存储器件提供具有高电阻和低电阻分量的均衡电路。 均衡电路限制电流，即使发生字线数字短路。

公开(公告)号：US20050099836A1

公开(公告)日：2005-05-12

申请号：US10998483

申请日：2004-11-29

申请人： Luan Tran ,  Stephen Porter ,  Scot Graham ,  Steven Howell

发明人： Luan Tran ,  Stephen Porter ,  Scot Graham ,  Steven Howell

IPC分类号： G11C7/12 ,  G11C7/18 ,  G11C11/4097 ,  G11C11/24 ,  G11C5/06

CPC分类号： G11C7/02 ,  G11C7/12 ,  G11C7/18 ,  G11C11/401 ,  G11C11/4097 ,  G11C29/816 ,  G11C2207/002 ,  G11C2207/005 ,  Y10S257/906

摘要： A memory device includes isolation devices located between memory cells. A plurality of isolation lines connects the isolation devices to a positive voltage during normal operations but still keeps the isolation devices in the off state to provide isolation between the memory cells. A current control circuit is placed between the isolation lines and a power node for reducing a current flowing between the isolation lines and the power node in case a deflect occurs at any one of isolation devices.

摘要翻译： 存储器件包括位于存储器单元之间的隔离器件。 多个隔离线在正常操作期间将隔离装置连接到正电压，但是仍然使隔离装置保持在关闭状态以提供存储单元之间的隔离。 在隔离线路和电源节点之间放置电流控制电路，用于在任何一个隔离装置发生偏转的情况下减少在隔离线路与功率节点之间流动的电流。

公开(公告)号：US5031062A

公开(公告)日：1991-07-09

申请号：US643446

申请日：1991-01-18

申请人： Joseph A. Wood ,  Dennis Ogden ,  Scot Graham

发明人： Joseph A. Wood ,  Dennis Ogden ,  Scot Graham

IPC分类号： G11B17/02 ,  G11B17/038 ,  G11B23/00

CPC分类号： G11B17/02 ,  G11B17/038 ,  G11B23/0021

摘要： A method for assembling disks in a disk drive apparatus is disclosed, as well as the resultant assembly. The method reduces the occurrence of disk head crashes resulting from penetration of the air bearing on which the disk head rides because of one or more surface irregularities found in the disk surface at or near inner diameter portions of the disk which lead to rippling of the disk surface. The elimination or reduction in size of the surface irregularities is achieved using a flowable filler material that is received by the surface irregularities and remains therein after the disk or disks are clamped to a spindle. The filler material is preferably an adhesive and it reduces any differences in the surface topography of the disk and the accompanying clamping-related parts. Bowing of the disk at its inner diameter portions due to uneven clamping forces is also reduced in the present invention. The resultant assembly has particular utility for use with smaller diameter disks having a diameter of about 95 mm or less.

摘要翻译： 公开了一种用于在盘驱动装置中组装盘的方法，以及所得到的组件。 该方法减少了由于在磁盘的内径部分处的盘表面中或附近发现导致盘的波纹的一个或多个表面不规则性而导致由于磁头头所在的空气轴承的穿透而导致的磁盘头崩溃的发生 表面。 表面凹凸的尺寸的消除或减小是通过使表面凹凸不平的可流动的填充材料实现的，并且在盘或盘被夹紧到主轴之后保持在其中。 填充材料优选是粘合剂，并且其减小了盘的表面形貌和伴随的夹紧相关部件的任何差异。 在本发明中，由于不均匀的夹紧力，在其内径部分处的盘的弯曲也减少了。 所得到的组件具有用于直径为约95mm或更小的较小直径圆盘的特别实用性。