公开(公告)号：US5629240A

公开(公告)日：1997-05-13

申请号：US462400

申请日：1995-06-05

申请人： Deviprasad Malladi ,  Shahid S. Ansari ,  Eric Bogatin

发明人： Deviprasad Malladi ,  Shahid S. Ansari ,  Eric Bogatin

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L23/50 ,  H01L23/528 ,  H01L23/64 ,  H01L25/16 ,  H01L21/60

CPC分类号： H01L23/642 ,  H01L23/50 ,  H01L23/5286 ,  H01L24/49 ,  H01L25/16 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/4911 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011

摘要： Switching noise at integrated circuit V.sub.DD and V.sub.SS metal traces is reduced by minimizing lead inductance in on-chip bypass capacitors. For each on-chip bypass capacitor, a pair of V.sub.DD -carrying and V.sub.SS -carrying metal traces is formed, these traces having regions spaced-apart laterally a distance .DELTA.X corresponding to lateral separation of the bypass capacitor connecting pads. For each bypass capacitor, column-shaped openings, spaced-apart distance .DELTA.X, are formed through the passivation and inter-metal oxide layers, as needed. These openings expose and access regions of the pair of spaced-apart metal traces carrying V.sub.SS and V.sub.DD. These openings, which may be formed after the IC has been fabricated, preferably are formed using focussed ion beam technology ("FIB"). Alternatively, these openings may be formed using masking and etching steps. The column-shaped openings are then made into conductive columnar elements, preferably using FIB deposition of tungsten or platinum. Conductive element pads are formed atop the conductive columnar elements at the outer surface of the IC passivation layer. The bypass capacitors are then attached to the IC, and the capacitor connecting pads are electrically connected to the respective conductive element pads using conductive epoxy or solder. This direct attachment of the on-chip bypass capacitors reduces effective capacitance lead inductance and improves attenuation of on-chip switching noise.

摘要翻译： 通过最小化片上旁路电容的引线电感，降低集成电路VDD和VSS金属走线的开关噪声。 对于每个片上旁路电容器，形成一对带VDD和VSS的金属迹线，这些迹线具有横向间隔开的距离为对应于旁路电容器连接焊盘的横向分离的距离DELTA X的区域。 对于每个旁路电容器，根据需要通过钝化和金属间氧化物层形成间隔开的距离DELTA X的柱状开口。 这些开口暴露并接近承载VSS和VDD的一对间隔开的金属迹线的区域。 可以在IC制造之后形成的这些开口优选地使用聚焦离子束技术（“FIB”）形成。 或者，这些开口可以使用掩模和蚀刻步骤形成。 然后将柱状开口制成导电柱状元件，优选使用FIB沉积钨或铂。 导电元件焊盘形成在IC钝化层的外表面上的导电柱状元件顶上。 然后将旁路电容器连接到IC，并且使用导电环氧树脂或焊料将电容器连接焊盘电连接到相应的导电元件焊盘。 片上旁路电容器的直接连接降低了有效的电容引线电感，并改善了片上开关噪声的衰减。

公开(公告)号：US6163866A

公开(公告)日：2000-12-19

申请号：US282913

申请日：1994-07-29

申请人： Shahid S. Ansari

发明人： Shahid S. Ansari

IPC分类号： G01R31/26 ,  G01R31/00 ,  G01R31/28 ,  G01R31/319 ,  H01L21/66

CPC分类号： G01R31/2808 ,  G01R31/2886 ,  G01R31/31905 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and apparatus for testing an integrated circuit in a system level environment such that the integrated circuit to be tested is wired into a system or module when the testing occurs is disclosed. In one embodiment of a method aspect of the invention, a die in a packaged integrated circuit to be tested is exposed. A module that incorporates the exposed die is placed on a test platform. The test platform and a sensor probe are relatively positioned such that the sensor probe can directly monitor the exposed die during testing. The positioning may be accomplished by moving the test platform, the sensor probe or both. The system is then driven in a manner which exercises the exposed die. The sensor probe then directly monitor the die while the exposed die is being exercised. The die can be exposed in a variety of manners as for example by removing a package cover or by etching portions of the plastic packaging material. An integrated circuit tester suitable for implementing this process is also disclosed as well as a test board suitable for use when the integrated circuits being tested are cavity down packaged integrated circuits.

摘要翻译： 一种用于在系统级环境中测试集成电路的方法和装置，使得当发生测试时将要测试的集成电路连接到系统或模块中。 在本发明的方法方面的一个实施例中，暴露出待测试的封装集成电路中的管芯。 将暴露的裸片并入的模块放置在测试平台上。 测试平台和传感器探头相对定位，使得传感器探头可以在测试期间直接监控裸露的裸片。 定位可以通过移动测试平台，传感器探头或两者来完成。 然后以一种锻炼暴露模具的方式驱动该系统。 传感器探针然后直接监控裸露，同时裸露的裸片正在运行。 模具可以以各种方式暴露，例如通过移除包装盖或通过蚀刻塑料包装材料的部分。 还公开了适用于实现该方法的集成电路测试器，以及适用于当被测试的集成电路是空腔封装集成电路时使用的测试板。

公开(公告)号：US5780930A

公开(公告)日：1998-07-14

申请号：US792088

申请日：1997-01-31

申请人： Deviprasad Malladi ,  Shahid S. Ansari ,  Eric Bogatin

发明人： Deviprasad Malladi ,  Shahid S. Ansari ,  Eric Bogatin

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L23/50 ,  H01L23/528 ,  H01L23/64 ,  H01L25/16 ,  H01L23/48 ,  H01G4/005 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/642 ,  H01L23/50 ,  H01L23/5286 ,  H01L24/49 ,  H01L25/16 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/4911 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011

摘要： Switching noise at integrated circuit V.sub.DD and V.sub.SS metal traces is reduced by minimizing lead inductance in on-chip bypass capacitors. For each on-chip bypass capacitor, a pair of V.sub.DD -carrying and V.sub.SS -carrying metal traces is formed, these traces having regions spaced-apart laterally a distance .DELTA.X corresponding to lateral separation of the bypass capacitor connecting pads. For each bypass capacitor, column-shaped openings, spaced-apart distance .DELTA.X, are formed through the passivation and inter-metal oxide layers, as needed. These openings expose and access regions of the pair of spaced-apart metal traces carrying V.sub.SS and V.sub.DD. These openings, which may be formed after the IC has been fabricated, preferably are formed using focussed ion beam technology ("FIB"). Alternatively, these openings may be formed using masking and etching steps. The column-shaped openings are then made into conductive columnar elements, preferably using FIB deposition of tungsten or platinum. Conductive element pads are formed atop the conductive columnar elements at the outer surface of the IC passivation layer. The bypass capacitors are then attached to the IC, and the capacitor connecting pads are electrically connected to the respective conductive element pads using conductive epoxy or other conductive bond material. This direct attachment of the on-chip bypass capacitors reduces effective capacitance lead inductance and improves attenuation of on-chip switching noise.

摘要翻译： 通过最小化片上旁路电容的引线电感，降低集成电路VDD和VSS金属走线的开关噪声。 对于每个片上旁路电容器，形成一对带VDD和VSS的金属迹线，这些迹线具有横向间隔开的距离为对应于旁路电容器连接焊盘的横向分离的距离DELTA X的区域。 对于每个旁路电容器，根据需要通过钝化和金属间氧化物层形成间隔开的距离DELTA X的柱状开口。 这些开口暴露并接近承载VSS和VDD的一对间隔开的金属迹线的区域。 可以在IC制造之后形成的这些开口优选地使用聚焦离子束技术（“FIB”）形成。 或者，这些开口可以使用掩模和蚀刻步骤形成。 然后将柱状开口制成导电柱状元件，优选使用FIB沉积钨或铂。 导电元件焊盘形成在IC钝化层的外表面上的导电柱状元件顶上。 然后将旁路电容器附接到IC，并且电容器连接焊盘使用导电环氧树脂或其它导电粘合材料电连接到相应的导电元件焊盘。 片上旁路电容器的直接连接降低了有效的电容引线电感，并改善了片上开关噪声的衰减。