公开(公告)号：US6096576A

公开(公告)日：2000-08-01

申请号：US920122

申请日：1997-09-02

申请人： Dave B. Corbin ,  Eric Bogatin

发明人： Dave B. Corbin ,  Eric Bogatin

IPC分类号： G02B5/18 ,  B81C3/00 ,  H01L21/98 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L21/44

CPC分类号： H01L25/50 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/06579 ,  H01L2225/06593 ,  H01L2924/3011

摘要： A method of and an apparatus for electrically interconnecting two integrated circuits devices includes mounting the two devices face to face. A first device is mounted for example to a substrate or lead frame. The first device includes a plurality of electrical/physical mounting structures preferably positioned along one edge. The mounting structure provide both electrical interconnection and physical mounting. A second device includes a corresponding plurality of mounting structures configured as a mirror image of the mounting structures on the first device. The mounting structures on the second device are also positioned along one of its edges so that once the mounting structures are brought together in a face to face relationship, the second device cantilevers off the edge of the first device. Under certain circumstances, a dummy block can be mounted to the substrate adjacent to the first device to act as a strut or support for the second device. The mounting structures can be positioned sufficiently close to one another that surface area consumed for I/O is minimized. Another set of electrical interconnect structures can be formed on the surface of the second device on the edge opposite the mounting structures. Electrical connection can be formed to these electrical interconnect structures using conventional techniques such as tape automated bonding.

摘要翻译： 用于电连接两个集成电路器件的方法和装置包括面对面地安装两个器件。 第一装置例如安装到基板或引线框架上。 第一装置包括优选沿着一个边缘定位的多个电/物理安装结构。 安装结构提供电气互连和物理安装。 第二装置包括配置为第一装置上的安装结构的镜像的对应的多个安装结构。 第二装置上的安装结构也沿着其一个边缘定位，使得一旦安装结构以面对面的关系将其组合在一起，则第二装置悬挂在第一装置的边缘上。 在某些情况下，可以将伪块安装到与第一装置相邻的基板上，以用作第二装置的支柱或支撑件。 安装结构可以彼此靠近地定位，使得I / O消耗的表面积最小化。 可以在与安装结构相对的边缘上的第二装置的表面上形成另一组电互连结构。 可以使用诸如胶带自动接合之类的常规技术来形成电连接到这些电互连结构。

公开(公告)号：US06452260B1

公开(公告)日：2002-09-17

申请号：US09500118

申请日：2000-02-08

申请人： Dave B. Corbin ,  Eric Bogatin

发明人： Dave B. Corbin ,  Eric Bogatin

IPC分类号： H01L2302

CPC分类号： H01L25/50 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06555 ,  H01L2225/06575 ,  H01L2225/06579 ,  H01L2225/06593 ,  H01L2924/3011

摘要： A method of and an apparatus for electrically interconnecting two integrated circuits devices includes mounting the two devices face to face. A first device is mounted for example to a substrate or lead frame. The first device includes a plurality of electrical/physical mounting structures preferably positioned along one edge. The mounting structure provide both electrical interconnection and physical mounting. A second device includes a corresponding plurality of mounting structures configured as a mirror image of the mounting structures on the first device. The mounting structures on the second device are also positioned along one of its edges so that once the mounting structures are brought together in a face to face relationship, the second device cantilevers off the edge of the first device. Under certain circumstances, a dummy block can be mounted to the substrate adjacent to the first device to act as a strut or support for the second device. The mounting structures can be positioned sufficiently close to one another that surface area consumed for I/O is minimized. Another set of electrical interconnect structures can be formed on the surface of the second device on the edge opposite the mounting structures. Electrical connection can be formed to these electrical interconnect structures using conventional techniques such as tape automated bonding.

摘要翻译： 用于电连接两个集成电路器件的方法和装置包括面对面地安装两个器件。 第一装置例如安装到基板或引线框架上。 第一装置包括优选沿着一个边缘定位的多个电/物理安装结构。 安装结构提供电气互连和物理安装。 第二装置包括配置为第一装置上的安装结构的镜像的对应的多个安装结构。 第二装置上的安装结构也沿着其一个边缘定位，使得一旦安装结构以面对面的关系将其组合在一起，则第二装置悬挂在第一装置的边缘上。 在某些情况下，可以将伪块安装到与第一装置相邻的基板上，以用作第二装置的支柱或支撑件。 安装结构可以彼此靠近地定位，使得I / O消耗的表面积最小化。 可以在与安装结构相对的边缘上的第二装置的表面上形成另一组电互连结构。 可以使用诸如胶带自动接合之类的常规技术来形成电连接到这些电互连结构。

公开(公告)号：US5780930A

公开(公告)日：1998-07-14

申请号：US792088

申请日：1997-01-31

申请人： Deviprasad Malladi ,  Shahid S. Ansari ,  Eric Bogatin

发明人： Deviprasad Malladi ,  Shahid S. Ansari ,  Eric Bogatin

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L23/50 ,  H01L23/528 ,  H01L23/64 ,  H01L25/16 ,  H01L23/48 ,  H01G4/005 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L23/642 ,  H01L23/50 ,  H01L23/5286 ,  H01L24/49 ,  H01L25/16 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/4911 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011

摘要： Switching noise at integrated circuit V.sub.DD and V.sub.SS metal traces is reduced by minimizing lead inductance in on-chip bypass capacitors. For each on-chip bypass capacitor, a pair of V.sub.DD -carrying and V.sub.SS -carrying metal traces is formed, these traces having regions spaced-apart laterally a distance .DELTA.X corresponding to lateral separation of the bypass capacitor connecting pads. For each bypass capacitor, column-shaped openings, spaced-apart distance .DELTA.X, are formed through the passivation and inter-metal oxide layers, as needed. These openings expose and access regions of the pair of spaced-apart metal traces carrying V.sub.SS and V.sub.DD. These openings, which may be formed after the IC has been fabricated, preferably are formed using focussed ion beam technology ("FIB"). Alternatively, these openings may be formed using masking and etching steps. The column-shaped openings are then made into conductive columnar elements, preferably using FIB deposition of tungsten or platinum. Conductive element pads are formed atop the conductive columnar elements at the outer surface of the IC passivation layer. The bypass capacitors are then attached to the IC, and the capacitor connecting pads are electrically connected to the respective conductive element pads using conductive epoxy or other conductive bond material. This direct attachment of the on-chip bypass capacitors reduces effective capacitance lead inductance and improves attenuation of on-chip switching noise.

摘要翻译： 通过最小化片上旁路电容的引线电感，降低集成电路VDD和VSS金属走线的开关噪声。 对于每个片上旁路电容器，形成一对带VDD和VSS的金属迹线，这些迹线具有横向间隔开的距离为对应于旁路电容器连接焊盘的横向分离的距离DELTA X的区域。 对于每个旁路电容器，根据需要通过钝化和金属间氧化物层形成间隔开的距离DELTA X的柱状开口。 这些开口暴露并接近承载VSS和VDD的一对间隔开的金属迹线的区域。 可以在IC制造之后形成的这些开口优选地使用聚焦离子束技术（“FIB”）形成。 或者，这些开口可以使用掩模和蚀刻步骤形成。 然后将柱状开口制成导电柱状元件，优选使用FIB沉积钨或铂。 导电元件焊盘形成在IC钝化层的外表面上的导电柱状元件顶上。 然后将旁路电容器附接到IC，并且电容器连接焊盘使用导电环氧树脂或其它导电粘合材料电连接到相应的导电元件焊盘。 片上旁路电容器的直接连接降低了有效的电容引线电感，并改善了片上开关噪声的衰减。

公开(公告)号：US5138149A

公开(公告)日：1992-08-11

申请号：US578538

申请日：1990-09-05

申请人： Raymond J. Cadet ,  Hung-Nan Chao ,  Sing-wing Hui ,  Eric Bogatin ,  Steven C. Leach

发明人： Raymond J. Cadet ,  Hung-Nan Chao ,  Sing-wing Hui ,  Eric Bogatin ,  Steven C. Leach

IPC分类号： G01J1/44 ,  G01N21/27

CPC分类号： H01J37/32963 ,  G01N21/27 ,  G01J2001/4406 ,  G01N21/4738 ,  G01N2201/0621 ,  G01N2201/1222 ,  G01N2201/124

摘要： A sensor board for use with an endpoint controller which monitors light intensity is provided. The sensor board can provide a dynamic range of up to five million because a constant current driver and phase sensitive detector help eliminate noise from the detected signal. The sensor board can also subtract a DC voltage offset from the detected signal and amplify the difference to provide increased resolution of small changes in the detected signal.

摘要翻译： 提供了一种用于监视光强度的端点控制器的传感器板。 传感器板可以提供高达500万的动态范围，因为恒定电流驱动器和相位敏感检测器有助于消除检测到的信号中的噪声。 传感器板还可以从检测到的信号中减去直流电压偏移，并放大差值，以提高检测信号的小变化分辨率。

公开(公告)号：US5629240A

公开(公告)日：1997-05-13

申请号：US462400

申请日：1995-06-05

申请人： Deviprasad Malladi ,  Shahid S. Ansari ,  Eric Bogatin

发明人： Deviprasad Malladi ,  Shahid S. Ansari ,  Eric Bogatin

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L23/50 ,  H01L23/528 ,  H01L23/64 ,  H01L25/16 ,  H01L21/60

CPC分类号： H01L23/642 ,  H01L23/50 ,  H01L23/5286 ,  H01L24/49 ,  H01L25/16 ,  H01L2224/16 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/4911 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011

摘要： Switching noise at integrated circuit V.sub.DD and V.sub.SS metal traces is reduced by minimizing lead inductance in on-chip bypass capacitors. For each on-chip bypass capacitor, a pair of V.sub.DD -carrying and V.sub.SS -carrying metal traces is formed, these traces having regions spaced-apart laterally a distance .DELTA.X corresponding to lateral separation of the bypass capacitor connecting pads. For each bypass capacitor, column-shaped openings, spaced-apart distance .DELTA.X, are formed through the passivation and inter-metal oxide layers, as needed. These openings expose and access regions of the pair of spaced-apart metal traces carrying V.sub.SS and V.sub.DD. These openings, which may be formed after the IC has been fabricated, preferably are formed using focussed ion beam technology ("FIB"). Alternatively, these openings may be formed using masking and etching steps. The column-shaped openings are then made into conductive columnar elements, preferably using FIB deposition of tungsten or platinum. Conductive element pads are formed atop the conductive columnar elements at the outer surface of the IC passivation layer. The bypass capacitors are then attached to the IC, and the capacitor connecting pads are electrically connected to the respective conductive element pads using conductive epoxy or solder. This direct attachment of the on-chip bypass capacitors reduces effective capacitance lead inductance and improves attenuation of on-chip switching noise.

摘要翻译： 通过最小化片上旁路电容的引线电感，降低集成电路VDD和VSS金属走线的开关噪声。 对于每个片上旁路电容器，形成一对带VDD和VSS的金属迹线，这些迹线具有横向间隔开的距离为对应于旁路电容器连接焊盘的横向分离的距离DELTA X的区域。 对于每个旁路电容器，根据需要通过钝化和金属间氧化物层形成间隔开的距离DELTA X的柱状开口。 这些开口暴露并接近承载VSS和VDD的一对间隔开的金属迹线的区域。 可以在IC制造之后形成的这些开口优选地使用聚焦离子束技术（“FIB”）形成。 或者，这些开口可以使用掩模和蚀刻步骤形成。 然后将柱状开口制成导电柱状元件，优选使用FIB沉积钨或铂。 导电元件焊盘形成在IC钝化层的外表面上的导电柱状元件顶上。 然后将旁路电容器连接到IC，并且使用导电环氧树脂或焊料将电容器连接焊盘电连接到相应的导电元件焊盘。 片上旁路电容器的直接连接降低了有效的电容引线电感，并改善了片上开关噪声的衰减。