公开(公告)号：US08145846B2

公开(公告)日：2012-03-27

申请号：US13194041

申请日：2011-07-29

申请人： Sung-Pack Hong ,  Hye-Jeong Nam ,  Se-Wook Na ,  Shea-Yun Lee ,  Tae-Beom Kim

发明人： Sung-Pack Hong ,  Hye-Jeong Nam ,  Se-Wook Na ,  Shea-Yun Lee ,  Tae-Beom Kim

IPC分类号： G06F13/38

CPC分类号： G11C16/26 ,  G06F12/0862 ,  G06F12/0866 ,  G06F2212/2022

摘要： Disclosed is a method for reading data in a memory system including a buffer memory and a nonvolatile memory, the method being comprised of: determining whether an input address in a read request is allocated to the buffer memory; determining whether a size of requested data is larger than a reference unless the input address is allocated to the buffer memory; and conducting a prefetch reading operation from the nonvolatile memory if the requested data size is larger than the reference.

摘要翻译： 公开了一种用于在包括缓冲存储器和非易失性存储器的存储器系统中读取数据的方法，该方法包括：确定读请求中的输入地址是否被分配给缓冲存储器; 确定所请求的数据的大小是否大于参考，除非所述输入地址被分配给所述缓冲存储器; 并且如果所请求的数据大小大于参考值，则从非易失性存储器进行预取读取操作。

公开(公告)号：US20110289264A1

公开(公告)日：2011-11-24

申请号：US13194041

申请日：2011-07-29

申请人： Sung-Pack Hong ,  Hye-Jeong Nam ,  Se-Wook Na ,  Shea-Yun Lee ,  Tae-Beom Kim

发明人： Sung-Pack Hong ,  Hye-Jeong Nam ,  Se-Wook Na ,  Shea-Yun Lee ,  Tae-Beom Kim

IPC分类号： G06F12/00

CPC分类号： G11C16/26 ,  G06F12/0862 ,  G06F12/0866 ,  G06F2212/2022

摘要： Disclosed is a method for reading data in a memory system including a buffer memory and a nonvolatile memory, the method being comprised of: determining whether an input address in a read request is allocated to the buffer memory; determining whether a size of requested data is larger than a reference unless the input address is allocated to the buffer memory; and conducting a prefetch reading operation from the nonvolatile memory if the requested data size is larger than the reference.

摘要翻译： 公开了一种用于在包括缓冲存储器和非易失性存储器的存储器系统中读取数据的方法，该方法包括：确定读请求中的输入地址是否被分配给缓冲存储器; 确定所请求的数据的大小是否大于参考，除非所述输入地址被分配给所述缓冲存储器; 并且如果所请求的数据大小大于参考值，则从非易失性存储器进行预取读取操作。

公开(公告)号：US07890550B2

公开(公告)日：2011-02-15

申请号：US11646501

申请日：2006-12-28

申请人： Myung-Jin Jung ,  Jang-Hwan Kim ,  Dong-Hyun Song ,  Shea-Yun Lee ,  Yeon-Jin Mo ,  Jae-Hyun Hwang

发明人： Myung-Jin Jung ,  Jang-Hwan Kim ,  Dong-Hyun Song ,  Shea-Yun Lee ,  Yeon-Jin Mo ,  Jae-Hyun Hwang

IPC分类号： G06F12/00 ,  G06F17/30

CPC分类号： G06F12/0246 ,  G06F2212/7205

摘要： Example embodiments provide a garbage collection method which includes applying a weight to each of at least two or more factors to calculate garbage collection costs. A hash table is configured using the calculated garbage collection costs. The method further includes searching a block having the lowest garbage collection cost from the hash table and performing garbage collection on the searched block.

摘要翻译： 示例性实施例提供了一种垃圾收集方法，其包括对至少两个或更多个因素中的每一个应用权重来计算垃圾收集成本。 使用计算的垃圾回收成本配置哈希表。 该方法还包括从哈希表中搜索具有最低垃圾回收成本的块，并在所搜索的块上执行垃圾回收。

公开(公告)号：US07716422B2

公开(公告)日：2010-05-11

申请号：US11601820

申请日：2006-11-20

申请人： Dong-kun Shin ,  Sang-lyul Min ,  Shea-yun Lee ,  Jang-hwan Kim ,  Dong-hyun Song ,  Jeong-eun Kim

发明人： Dong-kun Shin ,  Sang-lyul Min ,  Shea-yun Lee ,  Jang-hwan Kim ,  Dong-hyun Song ,  Jeong-eun Kim

IPC分类号： G06F12/00

CPC分类号： G06F12/0866 ,  G06F12/0246 ,  G06F2212/1036 ,  G06F2212/222 ,  G06F2212/282 ,  G06F2212/7211

摘要： Provided are a storage apparatus using a non-volatile memory as a cache and a method of operating the same, in which the non-volatile memory is used as the cache so as to preserve data even when electricity is interrupted. The storage apparatus using a non-volatile memory as a cache includes a main storage medium, the non-volatile memory being used as the cache of the main storage medium and having a stationary region and a non-stationary region divided according to whether data are fixed, and a block management unit managing blocks allocated in the non-volatile memory.

摘要翻译： 提供了使用非易失性存储器作为高速缓存的存储装置及其操作方法，其中使用非易失性存储器作为高速缓存，以便即使电力中断也可以保存数据。 使用非易失性存储器作为高速缓存的存储装置包括主存储介质，非易失性存储器用作主存储介质的高速缓存，并且具有根据数据是否被分割的静止区域和非平稳区域 以及块管理单元管理分配在非易失性存储器中的块。

公开(公告)号：US20090077304A1

公开(公告)日：2009-03-19

申请号：US12168778

申请日：2008-07-07

申请人： Sung-Pack Hong ,  Hye-Jeong Nam ,  Se-Wook Na ,  Shea-Yun Lee ,  Tae-Beom Kim

发明人： Sung-Pack Hong ,  Hye-Jeong Nam ,  Se-Wook Na ,  Shea-Yun Lee ,  Tae-Beom Kim

IPC分类号： G06F12/00 ,  G06F12/02

CPC分类号： G11C16/26 ,  G06F12/0862 ,  G06F12/0866 ,  G06F2212/2022

摘要： Disclosed is a method for reading data in a memory system including a buffer memory and a nonvolatile memory, the method being comprised of: determining whether an input address in a read request is allocated to the buffer memory; determining whether a size of requested data is larger than a reference unless the input address is allocated to the buffer memory; and conducting a prefetch reading operation from the nonvolatile memory if the requested data size is larger than the reference.

摘要翻译： 公开了一种用于在包括缓冲存储器和非易失性存储器的存储器系统中读取数据的方法，该方法包括：确定读请求中的输入地址是否被分配给缓冲存储器; 确定所请求的数据的大小是否大于参考，除非所述输入地址被分配给所述缓冲存储器; 并且如果所请求的数据大小大于参考值，则从非易失性存储器进行预取读取操作。

公开(公告)号：US20070226588A1

公开(公告)日：2007-09-27

申请号：US11748933

申请日：2007-05-15

申请人： Shea-Yun Lee ,  Dong-Hyun Song ,  Jang-Hwan Kim ,  Sang-Lyul Min

发明人： Shea-Yun Lee ,  Dong-Hyun Song ,  Jang-Hwan Kim ,  Sang-Lyul Min

IPC分类号： H03M13/00

CPC分类号： H03M13/09 ,  G06F11/1004 ,  G06F11/1068

摘要： A memory device detects and correct bit errors. The memory device includes cyclic redundancy check (CRC) and error correction code (ECC) circuits. The CRC circuit generates a write CRC code corresponding to data to be stored in memory cells. The ECC circuit generates an ECC code corresponding to the data and detecting and correcting a bit error of the data by means of the ECC code during a read operation. The CRC circuit generates a read CRC code corresponding to data corrected by the ECC circuit during the read operation, and detects a bit error of the data according to a comparison of the read CRC code and the write CRC code.

摘要翻译： 存储器件检测并纠正位错误。 存储器件包括循环冗余校验（CRC）和纠错码（ECC）电路。 CRC电路产生对应于要存储在存储器单元中的数据的写入CRC码。 ECC电路产生与数据相对应的ECC码，并且在读取操作期间通过ECC码检测和校正数据的位错误。 CRC电路在读取操作期间产生与由ECC电路校正的数据相对应的读取CRC码，并且根据读取的CRC码和写入CRC码的比较来检测数据的位错误。

公开(公告)号：US08001356B2

公开(公告)日：2011-08-16

申请号：US11565811

申请日：2006-12-01

申请人： Jung-Been Im ,  Hye-Young Kim ,  Young-Joon Choi ,  Dong-Gi Lee ,  Shea-Yun Lee

发明人： Jung-Been Im ,  Hye-Young Kim ,  Young-Joon Choi ,  Dong-Gi Lee ,  Shea-Yun Lee

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F2212/1036 ,  G06F2212/7211

摘要： Integrated circuit systems include a non-volatile memory device (e.g, flash EEPROM device) and a memory processing circuit. The memory processing circuit is electrically coupled to the non-volatile memory device. The memory processing circuit is configured to reallocate addressable space within the non-volatile memory device. This reallocation is performed by increasing a number of physical addresses within the non-volatile memory device that are reserved as redundant memory addresses, in response to a capacity adjust command received by the memory processing circuit.

摘要翻译： 集成电路系统包括非易失性存储器件（例如，快闪EEPROM器件）和存储器处理电路。 存储器处理电路电耦合到非易失性存储器件。 存储器处理电路被配置为重新分配非易失性存储器件内的可寻址空间。 响应于由存储器处理电路接收的容量调整命令，通过增加非易失性存储器件中被保留为冗余存储器地址的物理地址的数量来执行该重新分配。

公开(公告)号：US20110066800A1

公开(公告)日：2011-03-17

申请号：US12949936

申请日：2010-11-19

申请人： Dong-hyun Song ,  Hye-jeong Nam ,  Shea-yun Lee ,  Jae-hyun Hwang ,  Sung-pack Hong ,  Young-joon Choi ,  Dong-gi Lee

发明人： Dong-hyun Song ,  Hye-jeong Nam ,  Shea-yun Lee ,  Jae-hyun Hwang ,  Sung-pack Hong ,  Young-joon Choi ,  Dong-gi Lee

IPC分类号： G06F12/00

CPC分类号： G06F12/0873 ,  G06F3/0613 ,  G06F3/0656 ,  G06F3/068 ,  G06F2212/217 ,  G06F2212/283

摘要： A data storage system includes a non-volatile memory, a disc recording medium, a non-volatile memory buffer, operatively disposed between a host interface and the non-volatile memory, which stores a portion of data stored in the non-volatile memory, and a disc buffer, operatively disposed between the host interface and the disc recording medium, which stores a portion of data stored in the disc recording medium. The data storage system may be configured to receive an access address from a host operatively connected to the host interface, and sequentially determine whether the access address exists in one of the non-volatile memory buffer, the non-volatile memory, the disc buffer, and the disc recording medium, in that order.

摘要翻译： 数据存储系统包括可操作地设置在主机接口和非易失性存储器之间的非易失性存储器，盘记录介质，非易失性存储器缓冲器，其存储存储在非易失性存储器中的数据的一部分， 以及可操作地设置在主机接口和盘记录介质之间的盘缓冲器，其存储存储在盘记录介质中的数据的一部分。 数据存储系统可以被配置为从可操作地连接到主机接口的主机接收访问地址，并且顺序地确定访问地址是否存在于非易失性存储器缓冲器，非易失性存储器，盘缓冲器， 和盘记录介质。

公开(公告)号：US20080104308A1

公开(公告)日：2008-05-01

申请号：US11653986

申请日：2007-01-17

申请人： Yeon-Jin Mo ,  Jang-Hwan Kim ,  Dong-Hyun Song ,  Shea-Yun Lee ,  Jae-Hyun Hwang ,  Myung-Jin Jung

发明人： Yeon-Jin Mo ,  Jang-Hwan Kim ,  Dong-Hyun Song ,  Shea-Yun Lee ,  Jae-Hyun Hwang ,  Myung-Jin Jung

IPC分类号： G06F12/00

CPC分类号： G06F12/0246 ,  G06F12/0866 ,  G06F2212/1032 ,  G06F2212/1036 ,  G06F2212/222 ,  G06F2212/7205 ,  G06F2212/7211 ,  Y02D10/13

摘要： A method is for recovering a block mapping table in a system including a flash memory device, where the block mapping table utilizes address mapping in accordance with a wear-leveling scheme. The method includes reading block arrangement information from the flash memory device for the wear-leveling scheme, restoring the block mapping table with reference to allocation block information included in the block arrangement information and scanning address allocation information included in spare regions of erased blocks of the flash memory device with reference to erased block information included in the block arrangement information and updating the block mapping table in accordance with the scanned address allocation information.

摘要翻译： 一种方法是用于在包括闪速存储器件的系统中恢复块映射表，其中块映射表根据磨损均衡方案利用地址映射。 该方法包括从擦除平坦化方案的闪速存储器件读取块排列信息，参考包括在块排列信息中的分配块信息和包括在块排列信息的擦除块的备用区中的扫描地址分配信息来恢复块映射表 参考块排列信息中包含的擦除块信息，并根据扫描地址分配信息更新块映射表。

公开(公告)号：US08479077B2

公开(公告)日：2013-07-02

申请号：US11748933

申请日：2007-05-15

申请人： Shea-Yun Lee ,  Dong-Hyun Song ,  Jang-Hwan Kim ,  Sang-Lyul Min

发明人： Shea-Yun Lee ,  Dong-Hyun Song ,  Jang-Hwan Kim ,  Sang-Lyul Min

IPC分类号： H03M13/00

CPC分类号： H03M13/09 ,  G06F11/1004 ,  G06F11/1068

摘要： A memory device detects and correct bit errors. The memory device includes cyclic redundancy check (CRC) and error correction code (ECC) circuits. The CRC circuit generates a write CRC code corresponding to data to be stored in memory cells. The ECC circuit generates an ECC code corresponding to the data and detecting and correcting a bit error of the data by means of the ECC code during a read operation. The CRC circuit generates a read CRC code corresponding to data corrected by the ECC circuit during the read operation, and detects a bit error of the data according to a comparison of the read CRC code and the write CRC code.

摘要翻译： 存储器件检测并纠正位错误。 存储器件包括循环冗余校验（CRC）和纠错码（ECC）电路。 CRC电路产生对应于要存储在存储器单元中的数据的写入CRC码。 ECC电路产生与数据相对应的ECC码，并且在读取操作期间通过ECC码检测和校正数据的位错误。 CRC电路在读取操作期间产生与由ECC电路校正的数据相对应的读取CRC码，并且根据读取的CRC码和写入CRC码的比较来检测数据的位错误。