-
公开(公告)号：US20130146561A1
公开(公告)日：2013-06-13
申请号：US13313566
申请日：2011-12-07
IPC分类号： B05D5/12
CPC分类号： H01L21/823487 , H01L29/66666
摘要： A method of manufacturing vertical transistors includes steps of: forming a conductive layer on the surface of a substrate with a ditch and two support portions; removing the conductive layer on the bottom wall of the ditch and top walls of the support portions via anisotropic etching through a etch back process; forming an oxidized portion in the ditch; and etching the conductive layer to form two gates without contacting each other. By forming the conductive layer on the surface of the ditch and adopting selective etching of the etch back process, the problem of forming sub-trenches caused by lateral etching or uneven etching rate that might otherwise occur in the conventional etching process is prevented, and the risk of damaging metal wires caused by increasing etching duration also can be averted.
摘要翻译： 制造垂直晶体管的方法包括以下步骤：在沟槽和两个支撑部分的衬底的表面上形成导电层; 通过回蚀工艺通过各向异性蚀刻去除沟槽底壁上的导电层和支撑部分的顶壁; 在沟中形成氧化部分; 并且蚀刻导电层以形成两个栅极而不彼此接触。 通过在沟槽的表面上形成导电层并采用蚀刻回蚀工艺的选择性蚀刻，防止了在常规蚀刻工艺中可能发生的横向蚀刻或不均匀蚀刻速率引起的形成子沟槽的问题， 也可以避免由腐蚀持续时间增加引起的金属丝损伤的风险。
-
公开(公告)号：US20130130463A1
公开(公告)日：2013-05-23
申请号：US13301255
申请日：2011-11-21
IPC分类号： H01L21/02
CPC分类号： H01L28/92 , H01L27/1085
摘要： A method of manufacturing a charging capacity structure includes steps of: forming a first oxide layer, a support layer and a second oxide layer on a substrate in sequence; forming a plurality of etching holes on the surface of the second oxide layer in a matrix to run through the substrate that are spaced from each other at a selected distance; forming a plurality of pillar layers in the etching holes; removing the second oxide layer by etching; forming an etching protection layer on the surfaces of the support layer and pillar tubes that is formed at a thickness one half of the spaced distance between the etching holes such that the pillar tubes at diagonal locations form a self-calibration hole; and finally removing the first oxide layer from the self-calibration hole by etching. Through the self-calibration hole, the invention needn't to provide extra photoresists to form holes.
摘要翻译： 制造充电容量结构的方法包括以下步骤：依次在基板上形成第一氧化物层，支撑层和第二氧化物层; 在所述第二氧化物层的表面上以矩阵形成多个蚀刻孔以穿过所述基板，所述蚀刻孔以选定距离彼此间隔开; 在蚀刻孔中形成多个柱层; 通过蚀刻去除第二氧化物层; 在支撑层和支柱管的表面上形成蚀刻保护层，其形成为蚀刻孔之间间隔距离的一半的厚度，使得在对角线位置处的柱管形成自校准孔; 最后通过蚀刻从自校准孔中除去第一氧化物层。 通过自校准孔，本发明不需要提供额外的光致抗蚀剂来形成孔。
-
公开(公告)号：US08673730B2
公开(公告)日：2014-03-18
申请号：US13301255
申请日：2011-11-21
IPC分类号： H01L21/20
CPC分类号： H01L28/92 , H01L27/1085
摘要： A method of manufacturing a charging capacity structure includes steps of: forming a first oxide layer, a support layer and a second oxide layer on a substrate in sequence; forming a plurality of etching holes on the surface of the second oxide layer in a matrix to run through the substrate that are spaced from each other at a selected distance; forming a plurality of pillar layers in the etching holes; removing the second oxide layer by etching; forming an etching protection layer on the surfaces of the support layer and pillar tubes that is formed at a thickness one half of the spaced distance between the etching holes such that the pillar tubes at diagonal locations form a self-calibration hole; and finally removing the first oxide layer from the self-calibration hole by etching. Through the self-calibration hole, the invention needn't to provide extra photoresists to form holes.
摘要翻译： 制造充电容量结构的方法包括以下步骤：依次在基板上形成第一氧化物层，支撑层和第二氧化物层; 在所述第二氧化物层的表面上以矩阵形成多个蚀刻孔以穿过所述基板，所述蚀刻孔以选定距离彼此间隔开; 在蚀刻孔中形成多个柱层; 通过蚀刻去除第二氧化物层; 在支撑层和支柱管的表面上形成蚀刻保护层，其形成为蚀刻孔之间间隔距离的一半的厚度，使得在对角线位置处的柱管形成自校准孔; 最后通过蚀刻从自校准孔中除去第一氧化物层。 通过自校准孔，本发明不需要提供额外的光致抗蚀剂来形成孔。
-
公开(公告)号：US08613861B2
公开(公告)日：2013-12-24
申请号：US13313566
申请日：2011-12-07
IPC分类号： H01B13/00
CPC分类号： H01L21/823487 , H01L29/66666
摘要： A method of manufacturing vertical transistors includes steps of: forming a conductive layer on the surface of a substrate with a ditch and two support portions; removing the conductive layer on the bottom wall of the ditch and top walls of the support portions via anisotropic etching through a etch back process; forming an oxidized portion in the ditch; and etching the conductive layer to form two gates without contacting each other. By forming the conductive layer on the surface of the ditch and adopting selective etching of the etch back process, the problem of forming sub-trenches caused by lateral etching or uneven etching rate that might otherwise occur in the conventional etching process is prevented, and the risk of damaging metal wires caused by increasing etching duration also can be averted.
摘要翻译： 制造垂直晶体管的方法包括以下步骤：在沟槽和两个支撑部分的衬底的表面上形成导电层; 通过回蚀工艺通过各向异性蚀刻去除沟槽底壁上的导电层和支撑部分的顶壁; 在沟中形成氧化部分; 并且蚀刻导电层以形成两个栅极而不彼此接触。 通过在沟槽的表面上形成导电层并采用蚀刻回蚀工艺的选择性蚀刻，防止了在常规蚀刻工艺中可能发生的横向蚀刻或不均匀蚀刻速率引起的形成子沟槽的问题， 也可以避免由腐蚀持续时间增加引起的金属丝损伤的风险。
-
公开(公告)号：US08283715B2
公开(公告)日：2012-10-09
申请号：US12855436
申请日：2010-08-12
申请人： Yung-Chang Lin , Sheng-Chang Liang
发明人： Yung-Chang Lin , Sheng-Chang Liang
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L21/823487 , H01L27/10876 , H01L27/10885 , H01L27/10891 , H01L29/0642 , H01L29/0653 , H01L29/66666 , H01L29/7827
摘要： An integrated circuit with a memory cell is disclosed. The integrated circuit with a memory cell includes: a word line disposed in a word line trench of a substrate; a bit line disposed below the word line in a bit line trench and extending orthogonal to the word line; and, a separating layer disposed above the bit line in the bit line trench that separates the word line from the bit line; wherein an etching rate of the separating layer approaches that of the substrate.
摘要翻译： 公开了一种具有存储单元的集成电路。 具有存储单元的集成电路包括：设置在基板的字线沟槽中的字线; 布置在位线下方的字线下方且与字线正交延伸的位线; 以及分离层，其设置在所述位线沟槽中的位线之上，所述位线沟槽将所述字线与所述位线分离; 其中所述分离层的蚀刻速率接近所述衬底的蚀刻速率。
-
-
-
-
搜索结果
5 条记录 (耗时 0.011 秒)
