公开(公告)号：US20130146561A1

公开(公告)日：2013-06-13

申请号：US13313566

申请日：2011-12-07

申请人： Hsiao-chia Chen ,  Sheng-chang Liang ,  Chien-hua Tsai ,  Masahiko Ohuchi

发明人： Hsiao-chia Chen ,  Sheng-chang Liang ,  Chien-hua Tsai ,  Masahiko Ohuchi

IPC分类号： B05D5/12

CPC分类号： H01L21/823487 ,  H01L29/66666

摘要： A method of manufacturing vertical transistors includes steps of: forming a conductive layer on the surface of a substrate with a ditch and two support portions; removing the conductive layer on the bottom wall of the ditch and top walls of the support portions via anisotropic etching through a etch back process; forming an oxidized portion in the ditch; and etching the conductive layer to form two gates without contacting each other. By forming the conductive layer on the surface of the ditch and adopting selective etching of the etch back process, the problem of forming sub-trenches caused by lateral etching or uneven etching rate that might otherwise occur in the conventional etching process is prevented, and the risk of damaging metal wires caused by increasing etching duration also can be averted.

摘要翻译： 制造垂直晶体管的方法包括以下步骤：在沟槽和两个支撑部分的衬底的表面上形成导电层; 通过回蚀工艺通过各向异性蚀刻去除沟槽底壁上的导电层和支撑部分的顶壁; 在沟中形成氧化部分; 并且蚀刻导电层以形成两个栅极而不彼此接触。 通过在沟槽的表面上形成导电层并采用蚀刻回蚀工艺的选择性蚀刻，防止了在常规蚀刻工艺中可能发生的横向蚀刻或不均匀蚀刻速率引起的形成子沟槽的问题， 也可以避免由腐蚀持续时间增加引起的金属丝损伤的风险。

公开(公告)号：US07598023B2

公开(公告)日：2009-10-06

申请号：US11162909

申请日：2005-09-28

申请人： Yi-Tyng Wu ,  Shih-Hung Chen ,  Huai-Hsuan Tsai ,  Chih-Hung Cheng ,  Chien-Hua Tsai ,  Hsuan-Hsu Chen

发明人： Yi-Tyng Wu ,  Shih-Hung Chen ,  Huai-Hsuan Tsai ,  Chih-Hung Cheng ,  Chien-Hua Tsai ,  Hsuan-Hsu Chen

IPC分类号： G03F7/00

CPC分类号： G02F1/133502 ,  G02F1/133553 ,  G02F1/136277 ,  Y10S430/151

摘要： A process for fabricating a micro-display is provided. First, a wafer having a driving circuit thereon is provided. Then, a metallic reflective layer is formed on the wafer. Thereafter, an anti-reflection layer and a patterned photoresist layer are sequentially formed on the metallic reflective layer. Using the patterned photoresist layer as an etching mask, the anti-reflection layer and the metallic reflective layer are etched to form a trench pattern that exposes the surface of the wafer. After that, the patterned photoresist layer is removed. A dielectric layer is formed to cover the anti-reflection layer and fill the trench pattern. Then, a portion of the dielectric layer and the anti-reflection layer are removed to expose the surface of the metallic reflective layer.

摘要翻译： 提供一种制造微型显示器的方法。 首先，提供其上具有驱动电路的晶片。 然后，在晶片上形成金属反射层。 此后，在金属反射层上依次形成抗反射层和图案化的光致抗蚀剂层。 使用图案化的光致抗蚀剂层作为蚀刻掩模，对抗反射层和金属反射层进行蚀刻以形成暴露晶片表面的沟槽图案。 之后，去除图案化的光致抗蚀剂层。 形成介电层以覆盖抗反射层并填充沟槽图案。 然后，去除电介质层和抗反射层的一部分以露出金属反射层的表面。

公开(公告)号：US20070072130A1

公开(公告)日：2007-03-29

申请号：US11162909

申请日：2005-09-28

申请人： Yi-Tyng Wu ,  Shih-Hung Chen ,  Huai-Hsuan Tsai ,  Chih-Hung Cheng ,  Chien-Hua Tsai ,  Hsuan-Hsu Chen

发明人： Yi-Tyng Wu ,  Shih-Hung Chen ,  Huai-Hsuan Tsai ,  Chih-Hung Cheng ,  Chien-Hua Tsai ,  Hsuan-Hsu Chen

IPC分类号： G03F7/26

CPC分类号： G02F1/133502 ,  G02F1/133553 ,  G02F1/136277 ,  Y10S430/151

摘要： A process for fabricating a micro-display is provided. First, a wafer having a driving circuit thereon is provided. Then, a metallic reflective layer is formed on the wafer. Thereafter, an anti-reflection layer and a patterned photoresist layer are sequentially formed on the metallic reflective layer. Using the patterned photoresist layer as an etching mask, the anti-reflection layer and the metallic reflective layer are etched to form a trench pattern that exposes the surface of the wafer. After that, the patterned photoresist layer is removed. A dielectric layer is formed to cover the anti-reflection layer and fill the trench pattern. Then, a portion of the dielectric layer and the anti-reflection layer are removed to expose the surface of the metallic reflective layer.

摘要翻译： 提供一种制造微型显示器的方法。 首先，提供其上具有驱动电路的晶片。 然后，在晶片上形成金属反射层。 此后，在金属反射层上依次形成抗反射层和图案化的光致抗蚀剂层。 使用图案化的光致抗蚀剂层作为蚀刻掩模，对抗反射层和金属反射层进行蚀刻以形成暴露晶片表面的沟槽图案。 之后，去除图案化的光致抗蚀剂层。 形成介电层以覆盖抗反射层并填充沟槽图案。 然后，去除电介质层和抗反射层的一部分以露出金属反射层的表面。

公开(公告)号：US6150223A

公开(公告)日：2000-11-21

申请号：US287881

申请日：1999-04-07

申请人： Horng-Non Chern ,  Kun-Chi Lin ,  Alex Hou ,  Chien-Hua Tsai ,  Tsu-An Lin

发明人： Horng-Non Chern ,  Kun-Chi Lin ,  Alex Hou ,  Chien-Hua Tsai ,  Tsu-An Lin

IPC分类号： H01L21/60 ,  H01L21/8234 ,  H01L21/336 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/76

CPC分类号： H01L21/76897 ,  H01L21/823468

摘要： A method for forming a different width of gate spacer is disclosed. The method includes firstly forming a gate oxide layer on a semiconductor substrate. A polysilicon layer, a conductive layer, a first dielectric layer are formed in order on the gate oxide layer. The first dielectric layer, the conductive layer, the polysilicon layer, and the gate oxide layer are further etched using them as the interior gate and the peripheral gate. Next, second dielectric layer, third dielectric layer, and fourth dielectric layer are formed over the interior gate and the peripheral gate, and a first photoresist layer abuts the surface of the fourth dielectric layer of the interior circuit. Moreover, etching the fourth dielectric layer of peripheral gate to form a second spacer of peripheral gate, and etching the third dielectric layer of the peripheral gate are undertaken to form a first spacer of the peripheral gate. Removing the first photoresist layer and the fourth dielectric layer of the interior circuit, a fifth dielectric layer is formed on the third dielectric layer of the interior circuit. The fourth dielectric layer and the top surface of the second dielectric layer of the peripheral circuit are removed. The fifth dielectric layer is formed on the first dielectric layer and the third peripheral of the peripheral circuit, and then the second photoresist layer on the fifth dielectric layer, wherein the third photoresist layer is patterned as a bit-line contact via of the interior circuit and the bit-line contact vias of the peripheral circuit. Finally, anisotropically etching the third photoresist layer and the fifth dielectric layer, a bit-line to the substrate contact via and a bit-line to the gate contact via are formed inside the fifth dielectric layer.

摘要翻译： 公开了一种用于形成不同宽度的栅极间隔物的方法。 该方法包括首先在半导体衬底上形成栅氧化层。 在栅极氧化物层上依次形成多晶硅层，导电层，第一介电层。 使用它们作为内部栅极和外围栅极进一步蚀刻第一介电层，导电层，多晶硅层和栅极氧化物层。 接下来，在内部栅极和外围栅极上形成第二电介质层，第三电介质层和第四电介质层，并且第一光致抗蚀剂层邻接内部电路的第四电介质层的表面。 此外，蚀刻外围栅极的第四介电层以形成外围栅极的第二间隔物，并且蚀刻外围栅极的第三介电层以形成外围栅极的第一间隔物。 去除内部电路的第一光致抗蚀剂层和第四电介质层，在内部电路的第三电介质层上形成第五电介质层。 除去第四电介质层和外围电路的第二电介质层的顶表面。 第五电介质层形成在第一电介质层和外围电路的第三外围，然后形成在第五介电层上的第二光致抗蚀剂层，其中第三光致抗蚀剂层被图案化为内部电路的位线接触通孔 和外围电路的位线接触通孔。 最后，在第五介电层内形成各向异性蚀刻第三光致抗蚀剂层和第五电介质层，到基板接触通孔的位线和到栅极接触通孔的位线。

公开(公告)号：US08613861B2

公开(公告)日：2013-12-24

申请号：US13313566

申请日：2011-12-07

申请人： Hsiao-chia Chen ,  Sheng-chang Liang ,  Chien-hua Tsai ,  Masahiko Ohuchi

发明人： Hsiao-chia Chen ,  Sheng-chang Liang ,  Chien-hua Tsai ,  Masahiko Ohuchi

IPC分类号： H01B13/00

CPC分类号： H01L21/823487 ,  H01L29/66666

摘要： A method of manufacturing vertical transistors includes steps of: forming a conductive layer on the surface of a substrate with a ditch and two support portions; removing the conductive layer on the bottom wall of the ditch and top walls of the support portions via anisotropic etching through a etch back process; forming an oxidized portion in the ditch; and etching the conductive layer to form two gates without contacting each other. By forming the conductive layer on the surface of the ditch and adopting selective etching of the etch back process, the problem of forming sub-trenches caused by lateral etching or uneven etching rate that might otherwise occur in the conventional etching process is prevented, and the risk of damaging metal wires caused by increasing etching duration also can be averted.

摘要翻译： 制造垂直晶体管的方法包括以下步骤：在沟槽和两个支撑部分的衬底的表面上形成导电层; 通过回蚀工艺通过各向异性蚀刻去除沟槽底壁上的导电层和支撑部分的顶壁; 在沟中形成氧化部分; 并且蚀刻导电层以形成两个栅极而不彼此接触。 通过在沟槽的表面上形成导电层并采用蚀刻回蚀工艺的选择性蚀刻，防止了在常规蚀刻工艺中可能发生的横向蚀刻或不均匀蚀刻速率引起的形成子沟槽的问题， 也可以避免由腐蚀持续时间增加引起的金属丝损伤的风险。

公开(公告)号：US08673730B2

公开(公告)日：2014-03-18

申请号：US13301255

申请日：2011-11-21

申请人： Pei-Chun Hung ,  Li-Hsun Chen ,  Chien-hua Tsai ,  Masahiko Ohuchi ,  Sheng-chang Liang

发明人： Pei-Chun Hung ,  Li-Hsun Chen ,  Chien-hua Tsai ,  Masahiko Ohuchi ,  Sheng-chang Liang

IPC分类号： H01L21/20

CPC分类号： H01L28/92 ,  H01L27/1085

摘要： A method of manufacturing a charging capacity structure includes steps of: forming a first oxide layer, a support layer and a second oxide layer on a substrate in sequence; forming a plurality of etching holes on the surface of the second oxide layer in a matrix to run through the substrate that are spaced from each other at a selected distance; forming a plurality of pillar layers in the etching holes; removing the second oxide layer by etching; forming an etching protection layer on the surfaces of the support layer and pillar tubes that is formed at a thickness one half of the spaced distance between the etching holes such that the pillar tubes at diagonal locations form a self-calibration hole; and finally removing the first oxide layer from the self-calibration hole by etching. Through the self-calibration hole, the invention needn't to provide extra photoresists to form holes.

摘要翻译： 制造充电容量结构的方法包括以下步骤：依次在基板上形成第一氧化物层，支撑层和第二氧化物层; 在所述第二氧化物层的表面上以矩阵形成多个蚀刻孔以穿过所述基板，所述蚀刻孔以选定距离彼此间隔开; 在蚀刻孔中形成多个柱层; 通过蚀刻去除第二氧化物层; 在支撑层和支柱管的表面上形成蚀刻保护层，其形成为蚀刻孔之间间隔距离的一半的厚度，使得在对角线位置处的柱管形成自校准孔; 最后通过蚀刻从自校准孔中除去第一氧化物层。 通过自校准孔，本发明不需要提供额外的光致抗蚀剂来形成孔。

公开(公告)号：US08546220B1

公开(公告)日：2013-10-01

申请号：US13551919

申请日：2012-07-18

申请人： Isao Tanaka ,  Chien-hua Tsai

发明人： Isao Tanaka ,  Chien-hua Tsai

IPC分类号： H01L21/336

CPC分类号： H01L21/84 ,  H01L27/10885 ,  H01L27/1203

摘要： A method for fabricating buried bit lines comprises steps of: defining a plurality of parallel masked regions and a plurality of first etched regions each forming between any two neighboring masked regions on a surface of a substrate, and wherein the masked region is wider than the first etched region; etching the first etched regions to form a plurality of first trenches and a plurality of first pillars; forming two bit lines respectively on two sidewalls of each first trench; etching the first pillars to form a plurality of second pillars corresponding to the bit lines. The present invention uses a two-stage etching process to prevent pillars from bending or collapsing due to high aspect ratio. Moreover, the present invention has a simple process and is able to reduce cost and decrease cell size.

摘要翻译： 一种用于制造掩埋位线的方法包括以下步骤：限定多个平行掩蔽区域和多个第一蚀刻区域，每个第一蚀刻区域形成在衬底的表面上的任何两个相邻的掩蔽区域之间，并且其中所述掩蔽区域比所述第一蚀刻区域宽 蚀刻区域 蚀刻第一蚀刻区域以形成多个第一沟槽和多个第一柱; 分别在每个第一沟槽的两个侧壁上形成两个位线; 蚀刻第一柱以形成对应于位线的多个第二柱。 本发明使用两级蚀刻工艺来防止柱由于高纵横比而弯曲或折叠。 此外，本发明具有简单的过程，并且能够降低成本并减小单元尺寸。

公开(公告)号：US06204107B1

公开(公告)日：2001-03-20

申请号：US09208611

申请日：1998-12-08

申请人： Kuo-Chi Lin ,  Kuen-Yow Lin ,  Chien-Hua Tsai ,  Kun-Chi Lin

发明人： Kuo-Chi Lin ,  Kuen-Yow Lin ,  Chien-Hua Tsai ,  Kun-Chi Lin

IPC分类号： H01L218234

CPC分类号： H01L21/76831 ,  H01L21/76832

摘要： A method for forming a multi-layered liner on the sidewalls of a node contact opening includes the steps of providing a substrate having a dielectric layer thereon. The dielectric layer further includes a node contact opening that exposes a portion of the substrate. A first liner layer is then formed on the sidewalls of the node contact opening. Next, a second liner layer is formed over the first liner layer such that the first liner layer and the second liner layer together form a dual-layered liner. The first liner layer in contact with the dielectric layer has good insulation capacity while the second liner layer has good etch-resisting property.

摘要翻译： 在节点接触开口的侧壁上形成多层衬垫的方法包括以下步骤：提供其上具有介电层的衬底。 电介质层还包括暴露基板的一部分的节点接触开口。 然后在节点接触开口的侧壁上形成第一衬垫层。 接下来，在第一衬里层上形成第二衬里层，使得第一衬里层和第二衬里层一起形成双层衬垫。 与电介质层接触的第一衬垫层具有良好的绝缘能力，而第二衬垫层具有良好的抗蚀性能。

公开(公告)号：US20130237044A1

公开(公告)日：2013-09-12

申请号：US13416380

申请日：2012-03-09

申请人： Hsiao-chia CHEN ,  Chien-hua TSAI

发明人： Hsiao-chia CHEN ,  Chien-hua TSAI

IPC分类号： H01L21/283

CPC分类号： H01L21/823437 ,  H01L27/10876 ,  H01L27/10891 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66666 ,  H01L29/7827

摘要： A method of manufacturing metal gates comprises the steps of: forming a plurality of parallel trenches on a substrate; forming sequentially a conductive layer and a protective layer on the surfaces of the substrate and trenches; removing the protective layer and conductive layer on the surface of the substrate and the protective layer on the bottom walls of the trenches through anisotropic etching to retain only the protective layer and conductive layer on the side walls; and finally removing the conductive layer not covered by the protective layer through isotropic etching to retain only the protective layer and conductive layer on the side walls so that two insulating gates are respectively formed on the side walls. Thus no isolation material is needed to be disposed at the bottom of the trenches, and the problem of excessive etching to the trenches that results in undesirable insulation can be averted.

摘要翻译： 制造金属栅极的方法包括以下步骤：在衬底上形成多个平行的沟槽; 在基板和沟槽的表面上依次形成导电层和保护层; 通过各向异性蚀刻去除衬底表面上的保护层和导电层和沟槽底壁上的保护层，以仅保留侧壁上的保护层和导电层; 最后通过各向同性蚀刻去除未被保护层覆盖的导电层，仅在侧壁上保留保护层和导电层，从而在侧壁上分别形成两个绝缘栅。 因此，不需要将隔离材料设置在沟槽的底部，并且可以避免导致不希望的绝缘的对沟槽的过度蚀刻的问题。

公开(公告)号：US20130130463A1

公开(公告)日：2013-05-23

申请号：US13301255

申请日：2011-11-21

申请人： Pei-Chun HUNG ,  Li-Hsun CHEN ,  Chien-hua TSAI ,  Masahiko OHUCHI ,  Sheng-chang LIANG

发明人： Pei-Chun HUNG ,  Li-Hsun CHEN ,  Chien-hua TSAI ,  Masahiko OHUCHI ,  Sheng-chang LIANG

IPC分类号： H01L21/02

CPC分类号： H01L28/92 ,  H01L27/1085

摘要： A method of manufacturing a charging capacity structure includes steps of: forming a first oxide layer, a support layer and a second oxide layer on a substrate in sequence; forming a plurality of etching holes on the surface of the second oxide layer in a matrix to run through the substrate that are spaced from each other at a selected distance; forming a plurality of pillar layers in the etching holes; removing the second oxide layer by etching; forming an etching protection layer on the surfaces of the support layer and pillar tubes that is formed at a thickness one half of the spaced distance between the etching holes such that the pillar tubes at diagonal locations form a self-calibration hole; and finally removing the first oxide layer from the self-calibration hole by etching. Through the self-calibration hole, the invention needn't to provide extra photoresists to form holes.

摘要翻译： 制造充电容量结构的方法包括以下步骤：依次在基板上形成第一氧化物层，支撑层和第二氧化物层; 在所述第二氧化物层的表面上以矩阵形成多个蚀刻孔以穿过所述基板，所述蚀刻孔以选定距离彼此间隔开; 在蚀刻孔中形成多个柱层; 通过蚀刻去除第二氧化物层; 在支撑层和支柱管的表面上形成蚀刻保护层，其形成为蚀刻孔之间间隔距离的一半的厚度，使得在对角线位置处的柱管形成自校准孔; 最后通过蚀刻从自校准孔中除去第一氧化物层。 通过自校准孔，本发明不需要提供额外的光致抗蚀剂来形成孔。