公开(公告)号：US07277348B2

公开(公告)日：2007-10-02

申请号：US11356805

申请日：2006-02-17

申请人： Jack Zezhong Peng ,  David Fong ,  Harry Shengwen Luan ,  Jianguo Wang ,  Zhongshang Liu

发明人： Jack Zezhong Peng ,  David Fong ,  Harry Shengwen Luan ,  Jianguo Wang ,  Zhongshang Liu

IPC分类号： G11C17/18

CPC分类号： G11C17/16 ,  G11C2216/26

摘要： Memory cells including an SRAM and an OTP memory unit that combine the advantages of both technologies and can be fabricated by standard CMOS manufacturing without additional masking. The concepts and details may be applied to and utilized in other systems requiring memory and/or employing other fabrication technologies. Among other advantages, the SRAM part of memory cells allows countless programming of the cell, which is useful, for example, during the prototyping. The OTP part is utilized to permanently program the memory cell by either using external data or the data already existing in the SRAM part of the cell. The value held by the OTP unit may also be written directly into the SRAM part of the cell.

摘要翻译： 存储单元包括SRAM和OTP存储器单元，其结合了两种技术的优点，并且可以通过标准CMOS制造制造而不需要额外的掩蔽。 概念和细节可以应用于需要存储器和/或采用其它制造技术的其他系统中并被应用。 除了其他优点之外，存储器单元的SRAM部分允许对单元进行无数次的编程，这在原型设计中是有用的。 OTP部分用于通过使用外部数据或已经存在于单元的SRAM部分中的数据来永久地编程存储器单元。 OTP单元保存的值也可以直接写入单元的SRAM部分。

公开(公告)号：US5650964A

公开(公告)日：1997-07-22

申请号：US486192

申请日：1995-06-07

申请人： Jian Chen ,  James J. Hsu ,  Shengwen Luan ,  Yuan Tang ,  David Kuan-Yu Liu ,  Michael A. Van Buskirk

发明人： Jian Chen ,  James J. Hsu ,  Shengwen Luan ,  Yuan Tang ,  David Kuan-Yu Liu ,  Michael A. Van Buskirk

IPC分类号： G11C16/14 ,  G11C16/04

CPC分类号： G11C16/14

摘要： A process for discharging a floating gate semiconductor device formed in a semiconductor substrate, the device having a first active region, a second active region, a charge holding region, and a channel between the first and second active regions, the channel having a length defined by a distance below the charge holding region between the first and second active regions. The process comprises the steps of: applying a first positive voltage of about 4-8 volts to the first active region; applying a second voltage in the range of about 0.5-3 volts to the second active region; applying a third voltage in the range of minus 8 volts to the charge holding region; and coupling the substrate to ground. The first active region may comprise either a source or a drain region of a MOSFET, and the second active region may comprise a source region or a drain region of a MOSFET. In a further aspect an array of floating gate transistors, each transistor comprising a source, drain, gate and floating gate, each floating gate including an electric charge; and control logic coupled to the transistors, for selectively addressing the transistors is disclosed. In the apparatus, to discharge the floating gates of each transistor in the array: each source is coupled in common to a first voltage; each drain is coupled in common to a second voltage lower than the first voltage; the substrate is coupled to ground; and each floating gate is coupled to a negative voltage.

摘要翻译： 一种用于对形成在半导体衬底中的浮栅半导体器件进行放电的工艺，该器件具有第一有源区，第二有源区，电荷保持区和在第一和第二有源区之间的沟道， 在第一和第二有源区域之间的电荷保持区域之下的距离处。 该方法包括以下步骤：向第一有源区施加约4-8伏特的第一正电压; 向第二活动区域施加约0.5-3伏特范围内的第二电压; 将负8伏范围内的第三电压施加到电荷保持区; 并将衬底耦合到地面。 第一有源区可以包括MOSFET的源极或漏极区域，并且第二有源区域可以包括MOSFET的源极区域或漏极区域。 在另一方面，一种浮动栅极晶体管阵列，每个晶体管包括源极，漏极，栅极和浮置栅极，每个浮置栅极包括电荷; 并且公开了耦合到晶体管的控制逻辑，用于选择性寻址晶体管。 在该装置中，为了排出阵列中每个晶体管的浮置栅极：每个源极共同耦合到第一电压; 每个漏极共同耦合到低于第一电压的第二电压; 衬底耦合到地面; 并且每个浮动栅极耦合到负电压。

公开(公告)号：US20110298054A1

公开(公告)日：2011-12-08

申请号：US12802206

申请日：2010-06-02

申请人： Harry Shengwen Luan

发明人： Harry Shengwen Luan

IPC分类号： H01L27/112 ,  H01L29/78

CPC分类号： H01L27/112 ,  G11C17/16 ,  H01L27/11206

摘要： The present invention provides a programmable memory array including a plurality of memory cells. At least one and preferably each memory cell of the plurality of memory cells include an isolation layer formed of a dielectric material, a field effect transistor, and a programmable element. The programmable element includes a conductive gate, a gate insulator present beneath the conductive gate, and a semiconductor body present under the gate insulator. The semiconductor body of the programmable element is of a different doping type then the doping of the channel region of the field effect transistor. Apart from these components, the memory cell also includes a bit line connected to the source of the field effect transistor, a select word line connected to the gate of the field effect transistor and a program word line connected to the conductive gate of the programmable element.

摘要翻译： 本发明提供一种包括多个存储单元的可编程存储器阵列。 多个存储单元中的至少一个并且优选地每个存储单元包括由电介质材料形成的隔离层，场效应晶体管和可编程元件。 可编程元件包括导电栅极，存在于导电栅极下方的栅极绝缘体，以及存在于栅极绝缘体下方的半导体本体。 可编程元件的半导体本体具有不同的掺杂类型，然后掺杂场效应晶体管的沟道区。 除了这些部件之外，存储单元还包括连接到场效应晶体管的源极的位线，连接到场效应晶体管的栅极的选择字线和连接到可编程元件的导通栅极的编程字线 。

公开(公告)号：US08283731B2

公开(公告)日：2012-10-09

申请号：US12802206

申请日：2010-06-02

申请人： Harry Shengwen Luan

发明人： Harry Shengwen Luan

IPC分类号： H01L21/70

CPC分类号： H01L27/112 ,  G11C17/16 ,  H01L27/11206

摘要： The present invention provides a programmable memory array including a plurality of memory cells. At least one and preferably each memory cell of the plurality of memory cells include an isolation layer formed of a dielectric material, a field effect transistor, and a programmable element. The programmable element includes a conductive gate, a gate insulator present beneath the conductive gate, and a semiconductor body present under the gate insulator. The semiconductor body of the programmable element is of a different doping type then the doping of the channel region of the field effect transistor. Apart from these components, the memory cell also includes a bit line connected to the source of the field effect transistor, a select word line connected to the gate of the field effect transistor and a program word line connected to the conductive gate of the programmable element.

摘要翻译： 本发明提供一种包括多个存储单元的可编程存储器阵列。 多个存储单元中的至少一个并且优选地每个存储单元包括由电介质材料形成的隔离层，场效应晶体管和可编程元件。 可编程元件包括导电栅极，存在于导电栅极下方的栅极绝缘体，以及存在于栅极绝缘体下方的半导体本体。 可编程元件的半导体本体具有不同的掺杂类型，然后掺杂场效应晶体管的沟道区。 除了这些部件之外，存储单元还包括连接到场效应晶体管的源极的位线，连接到场效应晶体管的栅极的选择字线和连接到可编程元件的导通栅极的编程字线 。

公开(公告)号：US07623368B2

公开(公告)日：2009-11-24

申请号：US12330465

申请日：2008-12-08

申请人： Harry Shengwen Luan

发明人： Harry Shengwen Luan

IPC分类号： G11C7/08 ,  G11C7/00

CPC分类号： H01L29/7841 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/105 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/1203

摘要： A semiconductor memory structure based on gate oxide break down is constructed in a deep N-well. Thus, the electrical field over the programmable element during the transient procedure of gate oxide break down can be controlled to achieve the best memory programming results. The conductivity of the programmed memory cell is increased greatly and conductivity variation between the memory cells is reduced. This is achieved by adding a body bias during the programming process. The body here refers to a P-well formed within the deep N-Well. Furthermore, the read voltage offset is reduced greatly with this new memory configuration. These improved programming results will allow faster read speed and lower read voltage. This new structure also reduces current leakage from a memory array during programming.

摘要翻译： 基于栅极氧化物分解的半导体存储器结构构造在深N阱中。 因此，可以控制在栅极氧化物分解的过渡期间在可编程元件上的电场以实现最佳的存储器编程结果。 编程存储单元的电导率大大增加，并且存储单元之间的电导率变化减小。 这是通过在编程过程中增加体偏置来实现的。 这里的身体是指在深N井内形成的P井。 此外，使用这种新的存储器配置，读取电压偏移大大降低。 这些改进的编程结果将允许更快的读取速度和更低的读取电压。 这种新结构还减少了编程期间存储器阵列的电流泄漏。

公开(公告)号：US07586787B2

公开(公告)日：2009-09-08

申请号：US11858515

申请日：2007-09-20

申请人： Chinh Vo ,  Harry Shengwen Luan ,  Pearl Cheng

发明人： Chinh Vo ,  Harry Shengwen Luan ,  Pearl Cheng

IPC分类号： G11C16/04

CPC分类号： G11C7/12 ,  G11C16/10

摘要： In example embodiments, methods are provided for reducing bit line leakage current. In an example embodiment, an unselected program word line is biased to a bias voltage. The unselected program word line is connected to a memory cell and the memory cell includes a plurality of transistors. In another example embodiment, an unselected memory cell is biased to a negative bias voltage during read operations.

摘要翻译： 在示例实施例中，提供了用于减少位线泄漏电流的方法。 在示例实施例中，未选择的程序字线被偏置到偏置电压。 未选择的程序字线连接到存储单元，并且存储单元包括多个晶体管。 在另一个示例性实施例中，在读取操作期间将未选择的存储单元偏置到负偏置电压。

公开(公告)号：US06791891B1

公开(公告)日：2004-09-14

申请号：US10406406

申请日：2003-04-02

申请人： Jack Zezhong Peng ,  Harry Shengwen Luan ,  Jianguo Wang ,  Zhongshan Liu ,  David Fong ,  Fei Ye

发明人： Jack Zezhong Peng ,  Harry Shengwen Luan ,  Jianguo Wang ,  Zhongshan Liu ,  David Fong ,  Fei Ye

IPC分类号： G11C700

CPC分类号： G11C29/50 ,  G11C16/04 ,  G11C2029/5002

摘要： A method of testing a memory cell is disclosed. The memory cell has a data storage element constructed around an ultra-thin dielectric, such as a gate oxide, which is used to store information by stressing the ultra-thin dielectric into breakdown (soft or hard breakdown) to set the leakage current level of the memory cell. In order to ensure that the gate oxide underlying the data storage elements are of sufficient quality for programming, the memory cells of a memory array may be tested by applying a voltage across the gate oxide of the data storage element and measuring the current flow. Resultant current flow outside of a predetermined range indicates a defective memory cell.

摘要翻译： 公开了一种测试存储单元的方法。 存储单元具有围绕诸如栅极氧化物的超薄电介质构成的数据存储元件，其用于通过将超薄电介质压制成击穿（软或硬击穿）来存储信息，以设置泄漏电流水平 存储单元。 为了确保数据存储元件下面的栅极氧化物具有足够的编程质量，可以通过在数据存储元件的栅极氧化物上施加电压并测量电流来测试存储器阵列的存储单元。 在预定范围之外的所得电流表示有缺陷的存储单元。

公开(公告)号：US07173851B1

公开(公告)日：2007-02-06

申请号：US11252461

申请日：2005-10-18

申请人： John M. Callahan ,  Hemanshu T. Vernenker ,  Michael D. Fliesler ,  Glen Arnold Rosendale ,  Harry Shengwen Luan ,  Zhongshang Liu

发明人： John M. Callahan ,  Hemanshu T. Vernenker ,  Michael D. Fliesler ,  Glen Arnold Rosendale ,  Harry Shengwen Luan ,  Zhongshang Liu

IPC分类号： G11C11/34

CPC分类号： G11C17/18 ,  G11C17/16

摘要： A programmable memory cell formed useful in a memory array having column bitlines and row wordlines. The memory cell including a breakdown transistor having its gate connected to a program wordline and a write transistor connected in series at a sense node to said breakdown transistor. The gate of the write transistor is connected to a write wordline. Further, a first sense transistor has its gate connected to the sense node. A second sense transistor is connected in series to the first sense transistor and has its gate connected to a read wordline. The second sense transistor has its source connected to a column bitline.

摘要翻译： 形成在具有列位线和行字线的存储器阵列中有用的可编程存储器单元。 存储单元包括其栅极连接到程序字线的击穿晶体管和在感测节点处串联连接到所述击穿晶体管的写入晶体管。 写晶体管的栅极连接到写字线。 此外，第一感测晶体管的栅极连接到感测节点。 第二感测晶体管与第一感测晶体管串联连接，并且其栅极连接到读字线。 第二感测晶体管的源极连接到列位线。

公开(公告)号：US20090080275A1

公开(公告)日：2009-03-26

申请号：US11858515

申请日：2007-09-20

申请人： Chinh Vo ,  Harry Shengwen Luan ,  Pearl Cheng

发明人： Chinh Vo ,  Harry Shengwen Luan ,  Pearl Cheng

IPC分类号： G11C7/02

CPC分类号： G11C7/12 ,  G11C16/10

摘要： In example embodiments, methods are provided for reducing bit line leakage current. In an example embodiment, an unselected program word line is biased to a bias voltage. The unselected program word line is connected to a memory cell and the memory cell includes a plurality of transistors. In another example embodiment, an unselected memory cell is biased to a negative bias voltage during read operations.

摘要翻译： 在示例实施例中，提供了用于减少位线泄漏电流的方法。 在示例实施例中，未选择的程序字线被偏置到偏置电压。 未选择的程序字线连接到存储单元，并且存储单元包括多个晶体管。 在另一个示例性实施例中，在读取操作期间将未选择的存储单元偏置到负偏置电压。

公开(公告)号：US07471541B2

公开(公告)日：2008-12-30

申请号：US11759050

申请日：2007-06-06

申请人： David Fong ,  Jianguo Wang ,  Jack Zezhong Peng ,  Harry Shengwen Luan

发明人： David Fong ,  Jianguo Wang ,  Jack Zezhong Peng ,  Harry Shengwen Luan

IPC分类号： G11C7/00

CPC分类号： G11C7/08 ,  G11C7/18 ,  G11C16/28 ,  G11C2207/061 ,  G11C2207/065

摘要： Methods and apparatus for decreasing oxide stress and increasing reliability of memory transistors are disclosed. Duration and frequency of exposure of memory transistor gates to read signals are significantly reduced. In some embodiments, after a short read cycle, the content of the memory cell is latched and maintained as long as the subsequent read attempts are directed to the same memory cell. In these embodiments the read cycle need only be long enough to latch the memory content of the cell, and as long as the subsequent read attempts target the same memory cell the latched value will be used instead of repeating the read process.

摘要翻译： 公开了减少存储晶体管的氧化物应力和提高可靠性的方法和装置。 存储晶体管栅极对读取信号的持续时间和频率显着降低。 在一些实施例中，在短的读取周期之后，只要后续读取尝试被引导到相同的存储器单元，存储器单元的内容被锁存和维持。 在这些实施例中，读周期只需要足够长的时间来锁存单元的存储器内容，并且只要随后的读取尝试针对相同的存储单元，将使用锁存值而不是重复读取处理。