Digital phase locked loop clock recovery scheme
    1.
    发明授权
    Digital phase locked loop clock recovery scheme 失效
    数字锁相环时钟恢复方案

    公开(公告)号:US4821297A

    公开(公告)日:1989-04-11

    申请号:US123040

    申请日:1987-11-19

    摘要: A digital clock recovery scheme is disclosed. A reference clock, is used to provide a plurality of N signals with different clock phases. The incoming data stream is sampled and clocked with the reference clock to generate a plurality of M samples for each data bit. The logic values of the M samples are then analyzed to determine the relationship between the current clock phase and the data bit transition. In particular, if all samples agree, the clock phase is correctly aligned with the data. If the clock phase is either leading or lagging the data, various samples will disagree. In the latter situation, the clock phase is adjusted until all samples agree, the particular clock which provides this state thus being defined as the recovered clock signal.

    Method and apparatus for optimizing the transfer of data packets between
local area networks
    2.
    发明授权
    Method and apparatus for optimizing the transfer of data packets between local area networks 失效
    用于优化局域网之间数据包传输的方法和装置

    公开(公告)号:US6067300A

    公开(公告)日:2000-05-23

    申请号:US96110

    申请日:1998-06-11

    IPC分类号: H04L12/56 H04L12/28

    摘要: A switch apparatus for optimizing the transfer of data packets between a plurality of local area networks (LANs). Apparatus of the present invention are comprised of multiple independent controllers, e.g., a receive controller and a transmit controller, which share common resources including a first memory (a packet memory) which stores the data packets, a second memory (a descriptor memory) which stores pointers to the stored data packets, and buffered data paths (preferably using FIFO buffers). The independent controllers operate essentially concurrently for most tasks while interleaving their use of the shared resources. Consequently, embodiments of the present invention can simultaneously receive and transmit data across multiple LAN data ports (e.g., 28 Ethernet ports comprised of 10/100 and/or 10 Mbps ports).

    摘要翻译: 一种用于优化多个局域网(LAN)之间的数据分组传送的交换装置。 本发明的装置包括多个独立的控制器,例如接收控制器和发送控制器,其共享公共资源,包括存储数据分组的第一存储器(分组存储器),第二存储器(描述符存储器) 存储指向存储的数据分组的指针和缓冲的数据路径(优选地使用FIFO缓冲器)。 独立控制器对于大多数任务基本上同时进行操作,同时交替使用共享资源。 因此,本发明的实施例可以跨多个LAN数据端口(例如,由10/100和/或10Mbps端口组成的28个以太网端口)同时接收和发送数据。