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1.发明授权Method and apparatus for providing clock de-skewing on an integrated circuit board 失效在集成电路板上提供时钟去偏移的方法和装置
公开(公告)号：US5486783A
公开(公告)日：1996-01-23
申请号：US332202
申请日：1994-10-31
CPC分类号： H03L7/0812 , G06F1/10
摘要： The present invention relates to a circuit board having a plurality of integrated circuits provided thereon, wherein each integrated circuit (IC) receives a common clocked input reference signal and outputs a dam signal. Each integrated circuit is provided with a de-skewing circuit which compensates for signal delays in the IC so as to synchronize the output data signal with the clocked input reference signal. The de-skewing circuit is operative to generate a simulated signal delay to the input signal which emulates the signal delays of the IC.
摘要翻译： 本发明涉及一种具有设置在其上的多个集成电路的电路板，其中每个集成电路（IC）接收公共时钟输入参考信号并输出大坝信号。 每个集成电路设置有去偏移电路，其补偿IC中的信号延迟，以使输出数据信号与时钟输入参考信号同步。 去偏斜电路可操作以产生模拟IC的信号延迟的输入信号的模拟信号延迟。
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公开(公告)号：US5469438A
公开(公告)日：1995-11-21
申请号：US188623
申请日：1994-01-28
申请人： Robert J. Baumert , Clarence C. Joh
发明人： Robert J. Baumert , Clarence C. Joh
CPC分类号： H04L12/44
摘要： Briefly, in accordance with one embodiment of the invention, an extendible local area network includes a hub station including a memory and at least one hub station segment. The hub station segment is adapted to be coupled to at least N other hub station segments by a bi-directional control signal bus, N being a positive integer. The hub station segment includes at least two ports, each of the ports being adapted to receive electrical signal packet transmissions from a remote station. The memory and the hub station segment are mutually coupled by a signal bus. Likewise, a method of transmitting electrical signal packets in a hub station of an extendible local area hub network includes the steps of: receiving at least one electrical signal packet at one of the ports of one of the hub station segments in the hub station from a remote station directly coupled to the one hub station segment, transmitting the at least one packet to the memory from the one hub station segment, and receiving the at least one packet at any other hub station segment substantially concurrently with the transmission to the memory, at least if the at least one packet constitutes a unicast packet.
摘要翻译： 简而言之，根据本发明的一个实施例，可扩展局域网包括包括存储器和至少一个中心站段的中心站。 中心站段适于通过双向控制信号总线至少N个其他中心站段来耦合，N是正整数。 中心站段包括至少两个端口，每个端口适于从远程站接收电信号分组传输。 存储器和中心站段通过信号总线相互耦合。 类似地，在可扩展局域集线器网络的中心站中传输电信号分组的方法包括以下步骤：在中心站中的一个中心站段的一个端口处接收至少一个电信号分组， 远程站直接耦合到所述一个中心站段，从所述一个中心站段发送所述至少一个分组到所述存储器，并且在与所述传输基本同时地在所述另一个中心站段处接收所述至少一个分组到所述存储器， 至少如果所述至少一个分组构成单播分组。
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公开(公告)号：US5406592A
公开(公告)日：1995-04-11
申请号：US100522
申请日：1993-07-30
申请人： Robert J. Baumert
发明人： Robert J. Baumert
摘要： A circuit includes both a frequency locked loop (FLL) and a phase locked loop (PLL) to control the frequency and phase of a controlled oscillator with respect to a data signal. The FLL includes a frequency setting register that provides a digital control word to a digital-to-analog converter for causing the frequency of the controlled oscillator to equal the frequency of the data signal. The PLL has a phase detector for causing the phase of the controlled oscillator to approximate the phase of the data signal. The inventive circuit also includes a lock detector for determining whether the phase error between the controlled oscillator and the data signal is constant. When phase lock is achieved, a counter is enabled to count a periodic reference signal and to produce an overflow signal when a given count is exceeded. The overflow signal is selectively coupled to the frequency setting register in order to reduce the phase difference between the controlled oscillator and the data signal. In this manner, low phase error may be obtained in a first-order PLL system, thereby avoiding jitter peaking associated with second-order PLL systems.
摘要翻译： 电路包括锁相环（FLL）和锁相环（PLL），以控制受控振荡器相对于数据信号的频率和相位。 FLL包括频率设置寄存器，其向数模转换器提供数字控制字，以使受控振荡器的频率等于数据信号的频率。 PLL具有用于使受控振荡器的相位近似于数据信号的相位的相位检测器。 本发明的电路还包括用于确定受控振荡器和数据信号之间的相位误差是否恒定的锁定检测器。 当实现锁相时，计数器能够对周期性参考信号进行计数，并在超过给定计数时产生溢出信号。 溢出信号选择性地耦合到频率设置寄存器，以便减小受控振荡器和数据信号之间的相位差。 以这种方式，可以在一阶PLL系统中获得低相位误差，从而避免与二阶PLL系统相关的抖动峰化。
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公开(公告)号：US5448193A
公开(公告)日：1995-09-05
申请号：US290170
申请日：1994-08-15
摘要： An integrated circuit includes a clock alignment circuit having a frequency synthesizer for receiving a reference clock signal at a lower frequency and for generating phases of an oscillator clock signal at a higher frequency. The oscillator clock signal phases drive a desired clock signal generating circuit that generates various phases of the desired clock signal. The desired clock signal phases are systematically compared to the reference clock signal. The phase of the desired clock signal that is determined to align with the reference clock signal is provided as the desired clock signal output from the integrated circuit such that there is no apparent time delay through the integrated circuit. In an alternate embodiment, a single phase of the desired clock signal is selected and a phase locked loop adjusts the oscillator in the frequency synthesizer to align the selected phase of the desired clock signal with the reference clock signal.
摘要翻译： 集成电路包括具有频率合成器的时钟对准电路，频率合成器用于接收较低频率的参考时钟信号，并产生较高频率的振荡器时钟信号的相位。 振荡器时钟信号相位驱动期望的时钟信号产生电路，其产生所需时钟信号的各个相位。 所需的时钟信号相位与参考时钟信号进行系统比较。 被确定为与参考时钟信号对准的期望时钟信号的相位被提供为从集成电路输出的期望时钟信号，使得通过集成电路没有明显的时间延迟。 在替代实施例中，选择期望时钟信号的单相，并且锁相环调节频率合成器中的振荡器，以将期望时钟信号的所选相位与参考时钟信号对准。
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5.发明授权Method and apparatus for optimizing the transfer of data packets between local area networks 失效用于优化局域网之间数据包传输的方法和装置
公开(公告)号：US6067300A
公开(公告)日：2000-05-23
申请号：US96110
申请日：1998-06-11
CPC分类号： H04L49/9047 , H04L49/351 , H04L49/90 , H04L49/901 , H04L49/9042 , H04L49/9057 , H04L49/9089 , H04L49/3018 , H04L49/3027
摘要： A switch apparatus for optimizing the transfer of data packets between a plurality of local area networks (LANs). Apparatus of the present invention are comprised of multiple independent controllers, e.g., a receive controller and a transmit controller, which share common resources including a first memory (a packet memory) which stores the data packets, a second memory (a descriptor memory) which stores pointers to the stored data packets, and buffered data paths (preferably using FIFO buffers). The independent controllers operate essentially concurrently for most tasks while interleaving their use of the shared resources. Consequently, embodiments of the present invention can simultaneously receive and transmit data across multiple LAN data ports (e.g., 28 Ethernet ports comprised of 10/100 and/or 10 Mbps ports).
摘要翻译： 一种用于优化多个局域网（LAN）之间的数据分组传送的交换装置。 本发明的装置包括多个独立的控制器，例如接收控制器和发送控制器，其共享公共资源，包括存储数据分组的第一存储器（分组存储器），第二存储器（描述符存储器） 存储指向存储的数据分组的指针和缓冲的数据路径（优选地使用FIFO缓冲器）。 独立控制器对于大多数任务基本上同时进行操作，同时交替使用共享资源。 因此，本发明的实施例可以跨多个LAN数据端口（例如，由10/100和/或10Mbps端口组成的28个以太网端口）同时接收和发送数据。
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公开(公告)号：US5467351A
公开(公告)日：1995-11-14
申请号：US231419
申请日：1994-04-22
申请人： Robert J. Baumert
发明人： Robert J. Baumert
IPC分类号： G06F13/00 , H04L12/423 , H04L12/44 , H04J3/02
CPC分类号： H04L12/44 , H04L12/423
摘要： An extendible, round robin, local area hub station network includes: at least two round robin hub station segments coupled so as to form a ring-shaped hub station segment signal path. One of the two hub station segments includes a master hub station segment adapted to provide control signals, such as electrical or optical signals, on the ring-shaped segment signal path to transfer control of round robin polling over the hub station network between any two hub station segments in the hub station network. The hub station segments are also mutually coupled by a signal bus. Likewise, a method of round robin polling in an extendible, round robin, local area hub network includes the steps of: signaling a request for control of round robin polling over the hub station network from at least one of the at least two hub station segments in the hub station network to the master hub station segment, and transmitting a signal from the master hub station segment transferring control of round robin polling over the hub station network between any two of the at least two hub station segments.
摘要翻译： 可扩展的轮询局域中心站网络包括：至少两个循环中心站段被耦合以形成环形中心站段信号路径。 两个中心站段中的一个包括主集线器站段，其适于在环形段信号路径上提供诸如电信号或光信号的控制信号，以在任何两个集线器之间的中枢站网络上传送轮询轮询的控制 中心站网络中的站段。 中心站段也通过信号总线相互耦合。 类似地，在可扩展的循环局域网网络中的轮询轮询的方法包括以下步骤：从至少两个中心站段中的至少一个向中心站网络发信号通知控制轮询轮询的请求 在所述中心站网络中到所述主中心站段，以及在所述至少两个中心站段之间的任意两个之间通过所述中心站网络传送来自所述主中枢站段的信号，以传送轮询轮询的控制。
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公开(公告)号：US5392281A
公开(公告)日：1995-02-21
申请号：US165450
申请日：1993-12-13
CPC分类号： H04L12/6418 , H04L2012/6437 , H04L2012/6451 , H04L2012/6464 , H04L2012/6489
摘要： A hybrid ring network is disclosed having stations capable of transmitting and receiving packet and isochronous data. The ring stations include a latency adjustment buffer (LAB) which stores arriving packet data in one random access memory (PBUF) and both arriving packet and isochronous data in a separate random access memory (IBUF). For retransmission over the ring, packet data is read out only from the PBUF in accordance with the packet's retransmission priority. A LAB may be employed at a slave station and may be pre-programmed with a sufficient latency to compensate for an anticipated insertion or removal of a lobe, without changing the total latency of the ring. When a LAB is employed at a cycle master station the latency of the LAB is controlled by the total ring delay.
摘要翻译： 公开了具有能够发送和接收分组和同步数据的站的混合环网。 振铃站包括在一个随机存取存储器（PBUF）中存储到达的分组数据的延迟调整缓冲器（LAB）以及分离的随机存取存储器（IBUF）中的到达分组和同步数据。 为了在环上进行重传，根据分组的重传优先级，仅从PBUF读出分组数据。 可以在从站使用LAB，并且可以以足够的等待时间来预编程以补偿预期的叶片的插入或移除，而不改变环的总等待时间。 当在一个循环主站上使用LAB时，LAB的等待时间由整个环形延迟控制。
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