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    METHODS TO ACHIEVE 22 NANOMETER AND BEYOND WITH SINGLE EXPOSURE
    2.
    发明申请
    METHODS TO ACHIEVE 22 NANOMETER AND BEYOND WITH SINGLE EXPOSURE 审中-公开
    实现22纳米微粒的方法，并且单次曝光

    公开(公告)号：US20110193202A1

    公开(公告)日：2011-08-11

    申请号：US12701104

    申请日：2010-02-05

    Applicant: Vincent Yu ,  Shih-Che Wang ,  Chun-Kuang Chen

    Inventor： Vincent Yu ,  Shih-Che Wang ,  Chun-Kuang Chen

    IPC: H01L29/06 ,  G03F7/20

    CPC classification number: G03F1/22 ,  G03F1/20 ,  G03F1/32 ,  G03F7/325

    Abstract: Apparatus and methods are disclosed herein for fabricating semiconductor device features with a half-pitch node of 22 nm and beyond using single exposure and single etch (1P1E) photolithography techniques. The method includes exposing in a single exposure a photoresist layer to the exposure source through a photolithography mask where the photolithography mask has on it an island pattern of a material having high percentage transmission. The photoresist layer is developed using a negative tone developer to form a hole pattern in the photoresist layer. The 1P1E does not require the second photo exposure of the double patterning method. Furthermore, the method circumvents the island pattern collapsing issues and the need for strong illumination associated with exiting single 1P1E processes.

    Abstract translation: 本文公开了用于制造半导体器件特征的装置和方法，其半节距节点为22nm，并且超过使用单次曝光和单蚀刻（1P1E）光刻技术。 该方法包括通过光刻掩膜将光致抗蚀剂层暴露于曝光源到曝光源，光刻掩模在其上具有透光率高的材料的岛状图案。 使用负色调显影剂显影光致抗蚀剂层以在光致抗蚀剂层中形成孔图案。 1P1E不需要双重图案化方法的第二次曝光。 此外，该方法避免了岛屿模式的崩溃问题以及与退出单个1P1E过程相关的强烈照明的需求。

    Alignment mark design
    3.
    发明授权
    Alignment mark design 有权
    对齐标记设计

    公开(公告)号：US06420791B1

    公开(公告)日：2002-07-16

    申请号：US09448083

    申请日：1999-11-23

    Applicant: Chien-Chao Huang ,  Anseime Chen ,  Shih-Che Wang

    Inventor： Chien-Chao Huang ,  Anseime Chen ,  Shih-Che Wang

    IPC: H01L23544

    CPC classification number: H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

    Abstract: An alignment mark design has a metal plateau and a metal material formed over a substrate. The metal plateau is within a first dielectric layer. Openings within a second dielectric layer above the first dielectric layer are filled with a metal material. The metal material and the second dielectric layer alternate so that a part of the exposure light passing through the second dielectric layer between sections of the metal material can be reflected into an alignment system by the metal plateau.

    Abstract translation: 对准标记设计具有在基板上形成的金属平台和金属材料。 金属平台位于第一电介质层内。 在第一介电层上方的第二电介质层内的开口用金属材料填充。 金属材料和第二电介质层交替使得通过金属材料的部分之间通过第二介电层的曝光光的一部分可以通过金属平台反射到对准系统中。

    Method and apparatus for reducing spin-induced wafer charging
    5.
    发明申请
    Method and apparatus for reducing spin-induced wafer charging 审中-公开
    减少自旋晶片充电的方法和装置

    公开(公告)号：US20060000109A1

    公开(公告)日：2006-01-05

    申请号：US10884714

    申请日：2004-07-03

    Applicant: Hua-Tai Lin ,  Shih-Che Wang ,  Louie Liu ,  Chi-Hung Liao ,  Yi-Ming Dai

    Inventor： Hua-Tai Lin ,  Shih-Che Wang ,  Louie Liu ,  Chi-Hung Liao ,  Yi-Ming Dai

    IPC: C23G1/02 ,  F26B5/08 ,  F26B17/24

    CPC classification number: H01L21/67051 ,  B08B3/10 ,  H01L21/67028 ,  H01L21/67034

    Abstract: A novel method and apparatus for reducing or eliminating electrostatic charging of wafers during a spin-dry step of wafer cleaning is disclosed. The method includes rinsing a wafer, typically by dispensing a cleaning liquid such as deionized water on the wafer while spinning the wafer; and spin-drying the wafer by sequentially rotating the wafer in opposite directions. The apparatus includes a wafer support platform that is capable of sequentially rotating a wafer in opposite directions to spin-dry the wafer.

    Abstract translation: 公开了一种在晶片清洗的旋转干燥步骤中减少或消除晶片的静电充电的新型方法和装置。 该方法包括冲洗晶片，通常通过在旋转晶片的同时在晶片上分配诸如去离子水的清洁液体; 并通过沿相反方向顺序旋转晶片来旋转晶片。 该装置包括能够沿相反方向顺序旋转晶片以旋转晶片的晶片支撑平台。

    Method to form an alignment mark
    6.
    发明授权
    Method to form an alignment mark 有权
    形成对准标记的方法

    公开(公告)号：US6080659A

    公开(公告)日：2000-06-27

    申请号：US191306

    申请日：1998-11-13

    Applicant: Chia-Chen Chen ,  Shih-Che Wang

    Inventor： Chia-Chen Chen ,  Shih-Che Wang

    IPC: H01L21/3205 ,  H01L21/28 ,  H01L23/544 ,  H01L21/76

    CPC classification number: H01L23/544 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002

    Abstract: A method to form a better quality of an alignment pattern includes several steps, first starts from forming a polysilicon layer on a semiconductor substrate. Next, most of a central portion of the polysilicon layer is removed to expose the substrate. Then, an oxide layer is formed over the substrate and is patterned to form an opening, which exposes the substrate. A W layer is deposited over the substrate and is planarized by WCMP process to form a W plug inside the opening. A metal layer is formed over the substrate. The alignment mark pattern is formed on the metal layer.

    Abstract translation: 形成更好质量的取向图案的方法包括若干步骤，首先从在半导体衬底上形成多晶硅层开始。 接下来，去除多晶硅层的大部分中心部分以露出衬底。 然后，在衬底上形成氧化物层，并将其图案化以形成露出衬底的开口。 将W层沉积在衬底上并通过WCMP工艺平坦化，以在开口内形成W插头。 在衬底上形成金属层。 在金属层上形成对准标记图案。

    Structure Design and Fabrication on Photomask For Contact Hole Manufacturing Process Window Enhancement
    7.
    发明申请
    Structure Design and Fabrication on Photomask For Contact Hole Manufacturing Process Window Enhancement 有权
    用于接触孔制造工艺窗口增强的光掩模的结构设计和制造

    公开(公告)号：US20080131790A1

    公开(公告)日：2008-06-05

    申请号：US11565743

    申请日：2006-12-01

    Applicant: Ya Hui Chang ,  Tsiao Chen Wu ,  Shih-Che Wang

    Inventor： Ya Hui Chang ,  Tsiao Chen Wu ,  Shih-Che Wang

    IPC: G03F1/00 ,  G03F7/26

    CPC classification number: G03F1/32 ,  G03F1/36

    Abstract: The present disclosure provides a mask. The mask includes a substrate; a first attenuating layer disposed on the substrate, having a first material and a first thickness corresponding to a phase shift; and a second attenuating layer having a second material and disposed on the first attenuating layer. The first and second attenuating layers define a first feature having a first opening extending through the first and second attenuating layers; and a second feature having a second opening extending through the second attenuating layer and exposing the first attenuating layer. One of the first and second features is a main feature and the other one is an assistant feature proximate to the main feature.

    Abstract translation: 本公开提供了一种掩模。 掩模包括基底; 设置在所述基板上的第一衰减层，具有对应于相移的第一材料和第一厚度; 以及具有第二材料并设置在第一衰减层上的第二衰减层。 第一和第二衰减层限定第一特征，其具有延伸穿过第一和第二衰减层的第一开口; 以及具有延伸穿过第二衰减层并暴露第一衰减层的第二开口的第二特征。 第一和第二特征之一是主要特征，另一个是靠近主要特征的辅助功能。

    Structure design and fabrication on photomask for contact hole manufacturing process window enhancement
    9.
    发明授权
    Structure design and fabrication on photomask for contact hole manufacturing process window enhancement 有权
    用于接触孔制造工艺窗口增强的光掩模的结构设计和制造

    公开(公告)号：US07838173B2

    公开(公告)日：2010-11-23

    申请号：US11565743

    申请日：2006-12-01

    Applicant: Ya Hui Chang ,  Tsiao Chen Wu ,  Shih-Che Wang

    Inventor： Ya Hui Chang ,  Tsiao Chen Wu ,  Shih-Che Wang

    IPC: G03F1/00 ,  H01L21/00

    CPC classification number: G03F1/32 ,  G03F1/36

    Abstract: The present disclosure provides a mask. The mask includes a substrate; a first attenuating layer disposed on the substrate, having a first material and a first thickness corresponding to a phase shift; and a second attenuating layer having a second material and disposed on the first attenuating layer. The first and second attenuating layers define a first feature having a first opening extending through the first and second attenuating layers; and a second feature having a second opening extending through the second attenuating layer and exposing the first attenuating layer. One of the first and second features is a main feature and the other one is an assistant feature proximate to the main feature.

    Abstract translation: 本公开提供了一种掩模。 掩模包括基底; 设置在所述基板上的第一衰减层，具有对应于相移的第一材料和第一厚度; 以及具有第二材料并设置在第一衰减层上的第二衰减层。 第一和第二衰减层限定第一特征，其具有延伸穿过第一和第二衰减层的第一开口; 以及具有延伸穿过第二衰减层并暴露第一衰减层的第二开口的第二特征。 第一和第二特征之一是主要特征，另一个是靠近主要特征的辅助功能。

    System and method for critical dimension control in semiconductor manufacturing
    10.
    发明申请
    System and method for critical dimension control in semiconductor manufacturing 审中-公开
    半导体制造中关键尺寸控制的系统和方法

    公开(公告)号：US20060094131A1

    公开(公告)日：2006-05-04

    申请号：US10979515

    申请日：2004-11-02

    Applicant: Yu-Hsi Wang ,  Hua-Tai Lin ,  Chih-Ming Ke ,  Shih-Che Wang

    Inventor： Yu-Hsi Wang ,  Hua-Tai Lin ,  Chih-Ming Ke ,  Shih-Che Wang

    IPC: H01L21/66

    CPC classification number: G03F7/70558 ,  G03F7/70625 ,  H01L22/20

    Abstract: Provided are a system and method for modifying a fabrication process based on inline measurement information during manufacture of a semiconductor device. In one example, the method includes exposing a photoresist layer on the device, performing post-exposure baking on the photoresist layer, and obtaining at least one critical dimension (CD) measurement of the device. A determination may be made as to whether the CD measurement indicates that the exposure and/or baking step achieved a predefined result. If not, the device may be subjected to additional exposure or baking.

    Abstract translation: 提供了一种用于在制造半导体器件期间基于在线测量信息修改制造工艺的系统和方法。 在一个实例中，该方法包括在该器件上曝光光致抗蚀剂层，在该光致抗蚀剂层上进行曝光后烘烤，以及获得该器件的至少一个临界尺寸（CD）测量。 可以确定CD测量是否指示曝光和/或烘焙步骤达到预定的结果。 如果没有，则可以对该装置进行额外的曝光或烘烤。

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