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25 条记录 (耗时 0.053 秒)

    Advanced process control approach for Cu interconnect wiring sheet resistance control
    3.
    发明授权
    Advanced process control approach for Cu interconnect wiring sheet resistance control 失效
    Cu互连布线电阻控制的先进工艺控制方法

    公开(公告)号：US07083495B2

    公开(公告)日：2006-08-01

    申请号：US10723236

    申请日：2003-11-26

    申请人： Chun Hsien Lin ,  Ai-Sen Liu ,  Sunny Wu ,  Yu-Liang Lin ,  Henry Lo ,  Mei-Sheng Zhou

    发明人： Chun Hsien Lin ,  Ai-Sen Liu ,  Sunny Wu ,  Yu-Liang Lin ,  Henry Lo ,  Mei-Sheng Zhou

    IPC分类号： B24B49/00 ,  B24B1/00

    CPC分类号： B24B51/00 ,  B24B37/042 ,  G05B13/024 ,  H01L21/31053 ,  H01L21/3212

    摘要： A wafer based APC method for controlling an oxide (Cu, or TaN) polish step is described and combines a feed forward model that compensates for incoming wafer variations with a feed backward model which compensates for CMP variations. The method is geared toward minimizing Rs 3σ variations. A Rs target value is inputted with metrology data from previous processes that affects the width and thickness of the copper layer. A copper thickness target and polish time for the first wafer is determined. Post CMP measurement data of the first wafer is used to modify the polish rate with a disturbance factor and an updated polish time is computed for subsequent wafers. The CMP recipe for each wafer is adjusted with metrology data and post CMP measurements. The APC method is successful in controlling copper Rs variations for the 90 nm technology node and is independent of copper pattern density.

    摘要翻译： 描述了用于控制氧化物（Cu或TaN）抛光步骤的基于晶圆的APC方法，并且组合了用于补偿进入晶片变化的前馈模型与补偿CMP变化的馈送反向模型。 该方法面向最小化Rs 3sigma变化。 输入Rs目标值，其中来自先前工艺的测量数据影响铜层的宽度和厚度。 确定第一晶片的铜厚度目标和抛光时间。 第一晶片的CMP后测量数据被用于利用干扰因子修改抛光速率，并且为随后的晶片计算更新的抛光时间。 每个晶片的CMP配方用测量数据和后CMP测量进行调整。 APC方法成功地控制了90nm技术节点的铜Rs变化，并且与铜图案密度无关。

    Advanced process control approach for Cu interconnect wiring sheet resistance control
    4.
    发明申请
    Advanced process control approach for Cu interconnect wiring sheet resistance control 失效
    Cu互连布线电阻控制的先进工艺控制方法

    公开(公告)号：US20050112997A1

    公开(公告)日：2005-05-26

    申请号：US10723236

    申请日：2003-11-26

    申请人： Chun Lin ,  Ai-Sen Liu ,  Sunny Wu ,  Yu-Liang Lin ,  Henry Lo ,  Mei-Sheng Zhou

    发明人： Chun Lin ,  Ai-Sen Liu ,  Sunny Wu ,  Yu-Liang Lin ,  Henry Lo ,  Mei-Sheng Zhou

    IPC分类号： B24B37/04 ,  B24B51/00 ,  G05B13/02 ,  H01L21/3105 ,  H01L21/321 ,  B24B49/00 ,  B24B1/00

    CPC分类号： B24B51/00 ,  B24B37/042 ,  G05B13/024 ,  H01L21/31053 ,  H01L21/3212

    摘要： A wafer based APC method for controlling an oxide (Cu, or TaN) polish step is described and combines a feed forward model that compensates for incoming wafer variations with a feed backward model which compensates for CMP variations. The method is geared toward minimizing Rs 3σ variations. A Rs target value is inputted with metrology data from previous processes that affects the width and thickness of the copper layer. A copper thickness target and polish time for the first wafer is determined. Post CMP measurement data of the first wafer is used to modify the polish rate with a disturbance factor and an updated polish time is computed for subsequent wafers. The CMP recipe for each wafer is adjusted with metrology data and post CMP measurements. The APC method is successful in controlling copper Rs variations for the 90 nm technology node and is independent of copper pattern density.

    摘要翻译： 描述了用于控制氧化物（Cu或TaN）抛光步骤的基于晶圆的APC方法，并且组合了用于补偿进入晶片变化的前馈模型与补偿CMP变化的馈送反向模型。 该方法面向最小化Rs 3sigma变化。 输入Rs目标值，其中来自先前工艺的测量数据影响铜层的宽度和厚度。 确定第一晶片的铜厚度目标和抛光时间。 第一晶片的CMP后测量数据被用于利用干扰因子修改抛光速率，并且为随后的晶片计算更新的抛光时间。 每个晶片的CMP配方用测量数据和后CMP测量进行调整。 APC方法成功地控制了90nm技术节点的铜Rs变化，并且与铜图案密度无关。

    Method for forming dielectric barrier layer in damascene structure
    8.
    发明申请
    Method for forming dielectric barrier layer in damascene structure 失效
    在镶嵌结构中形成介质阻挡层的方法

    公开(公告)号：US20050051900A1

    公开(公告)日：2005-03-10

    申请号：US10657847

    申请日：2003-09-09

    申请人： Ai-Sen Liu ,  Syun-Ming Jang

    发明人： Ai-Sen Liu ,  Syun-Ming Jang

    IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/48

    CPC分类号： H01L21/76834 ,  H01L21/76801 ,  H01L21/76807 ,  H01L21/76826 ,  H01L21/76831 ,  H01L23/5222 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method for fabricating dielectric barrier layers in integrated circuit structures such as damascene structures is provided. In one embodiment, a low-k dielectric layer formed on a substrate is provided. The low-k dielectric layer has at least one opening exposing an underlying metal layer. A first silicon carbide barrier layer is formed to conformally cover the exposed surfaces of the opening. A portion of the first silicon carbide barrier layer above the low-k dielectric layer and over the bottom of the opening is converted with an oxidation treatment into a layer of silicon oxide. The silicon oxide layer is removed above the low-k dielectric layer and from the bottom of the opening. The opening is filled with a conductive layer in electrical contact with the underlying metal layer. The conductive layer is removed above the low-k dielectric layer to a predetermined depth below the low-k dielectric layer to define a recess therebelow. A second silicon carbide barrier layer is formed to cover the recess and above the low-k dielectric layer and the first silicon carbide barrier layer so as to seal the top of the structure. A portion of the second silicon carbide barrier layer above the low-k dielectric layer is converted with an oxidation treatment into a layer of silicon oxide. The layer of silicon oxide is then removed and the metal conductive layer is fully encapsulated by the silicon carbide barrier layer.

    摘要翻译： 提供了一种用于在诸如镶嵌结构的集成电路结构中制造介电阻挡层的方法。 在一个实施例中，提供了形成在衬底上的低k电介质层。 低k电介质层具有暴露下面的金属层的至少一个开口。 形成第一碳化硅阻挡层以保形地覆盖开口的暴露表面。 在低k电介质层上方和开口底部上的第一碳化硅阻挡层的一部分被氧化处理转化成氧化硅层。 在低k电介质层上方和从开口底部除去氧化硅层。 开口填充有与下面的金属层电接触的导电层。 将导电层在低k电介质层上方移除到低k电介质层下方的预定深度以限定其下方的凹部。 形成第二碳化硅阻挡层以覆盖凹部并且在低k电介质层和第一碳化硅阻挡层上方密封结构的顶部。 将低k电介质层上方的第二碳化硅阻挡层的一部分通过氧化处理转化为氧化硅层。 然后去除氧化硅层，并且金属导电层被碳化硅阻挡层完全包封。

    Method for multiple spacer width control
    9.
    发明授权
    Method for multiple spacer width control 有权
    多间隔宽度控制方法

    公开(公告)号：US07176137B2

    公开(公告)日：2007-02-13

    申请号：US10435009

    申请日：2003-05-09

    申请人： Baw-Ching Perng ,  Yih-Shung Lin ,  Ming-Ta Lei ,  Ai-Sen Liu ,  Chia-Hui Lin ,  Cheng-Chung Lin

    发明人： Baw-Ching Perng ,  Yih-Shung Lin ,  Ming-Ta Lei ,  Ai-Sen Liu ,  Chia-Hui Lin ,  Cheng-Chung Lin

    IPC分类号： H01L21/302

    CPC分类号： H01L29/6656 ,  H01L21/823468

    摘要： A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a first plurality of gate structures; blanket depositing a first dielectric layer over the first plurality of gate structures; blanket depositing a second dielectric layer over the first dielectric layer; etching back through a thickness of the first and second dielectric layers; blanket depositing a first photoresist layer to cover the first plurality and patterning to selectively expose at least a second plurality of gate structures; isotropically etching the at least a second plurality of gate structures for a predetermined time period to selectively etch away a predetermined portion of the first dielectric layer; and, selectively etching away the second dielectric layer to leave gate structures comprising a plurality of associated sidewall spacer widths.

    摘要翻译： 形成多个栅极侧壁间隔物的方法，每个栅极侧壁间隔件包括不同的相关栅极侧壁间隔物宽度，包括提供第一多个栅极结构; 在第一多个栅极结构上覆盖沉积第一介电层; 在第一介电层上铺设第二介电层; 通过第一和第二介电层的厚度回蚀; 覆盖沉积第一光致抗蚀剂层以覆盖第一多个并且图案化以选择性地暴露至少第二多个栅极结构; 对所述至少第二多个栅极结构进行各向同性蚀刻预定的时间段以选择性地蚀刻掉所述第一介电层的预定部分; 并且选择性地蚀刻掉第二介电层以留下包括多个相关联的侧壁间隔物宽度的栅极结构。

    Liquid crystal display panel
    10.
    发明申请
    Liquid crystal display panel 有权
    液晶显示面板

    公开(公告)号：US20060244887A1

    公开(公告)日：2006-11-02

    申请号：US11210854

    申请日：2005-08-25

    申请人： Tzu-Yuan Lin ,  Ren-Hung Huang ,  Po-Chang Wu ,  Shwu-Yun Tsay ,  Shune-Long Wu ,  Chia-Hsing Sun ,  Jin-Jei Wu ,  Po-Lun Chen ,  Ai-Sen Liu

    发明人： Tzu-Yuan Lin ,  Ren-Hung Huang ,  Po-Chang Wu ,  Shwu-Yun Tsay ,  Shune-Long Wu ,  Chia-Hsing Sun ,  Jin-Jei Wu ,  Po-Lun Chen ,  Ai-Sen Liu

    IPC分类号： G02F1/1343

    CPC分类号： G02F1/141 ,  G02F2001/134381 ,  G02F2001/13775

    摘要： An LCD panel including a first substrate, a second substrate and a smectic liquid crystal layer is disclosed. The first substrate includes a first electrode, a second electrode and a first horizontal alignment film. The first electrode has plural first portions. The second electrode has plural second portions. The first portions are spaced by the second portions. The electrical field directions formed between the first portions and the second portions are perpendicular to the surface of the first substrate. The electrical field direction on each first portion is opposite to that on each second portion. The first horizontal alignment film covers the first and the second electrodes. The second substrate includes a second horizontal alignment film. The horizontal rubbing direction of the first horizontal alignment film is parallel to that of the second horizontal alignment film. The smectic liquid crystal layer is sealed between the first and the second substrates.

    摘要翻译： 公开了一种包括第一基板，第二基板和近晶液晶层的LCD面板。 第一基板包括第一电极，第二电极和第一水平取向膜。 第一电极具有多个第一部分。 第二电极具有多个第二部分。 第一部分由第二部分隔开。 在第一部分和第二部分之间形成的电场方向垂直于第一基底的表面。 每个第一部分上的电场方向与每个第二部分上的电场方向相反。 第一水平取向膜覆盖第一和第二电极。 第二基板包括第二水平取向膜。 第一水平取向膜的水平摩擦方向与第二水平取向膜的水平摩擦方向平行。 层间液晶层被密封在第一和第二基板之间。