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32 条记录 (耗时 0.017 秒)

    Composition for hydrogen generation
    1.
    发明申请
    Composition for hydrogen generation 失效
    用于氢气生成的组成

    公开(公告)号：US20080305035A1

    公开(公告)日：2008-12-11

    申请号：US12156687

    申请日：2008-06-04

    申请人： Shih-Ying Hsu

    发明人： Shih-Ying Hsu

    IPC分类号： C01B3/08 ,  C09K3/00

    CPC分类号： B01J7/02 ,  C01B3/065 ,  Y02E60/362 ,  Y02E60/364

    摘要： A solid composition containing: (a) at least one metal hydride compound; (b) at least one borohydride compound; and (c) at least one of: (i) a transition metal halide, or (ii) a transition metal boride.

    摘要翻译： 一种固体组合物，其含有：（a）至少一种金属氢化物; （b）至少一种硼氢化合物; 和（c）至少一种：（i）过渡金属卤化物，或（ii）过渡金属硼化物。

    Method of fabricating static random access memory with spacers
    2.
    发明授权
    Method of fabricating static random access memory with spacers 失效
    使用间隔件制造静态随机存取存储器的方法

    公开(公告)号：US06326257B1

    公开(公告)日：2001-12-04

    申请号：US09782635

    申请日：2001-02-13

    申请人： Shih-Ying Hsu

    发明人： Shih-Ying Hsu

    IPC分类号： H01L218244

    CPC分类号： H01L27/11 ,  H01L27/1104

    摘要： A method of fabricating a static random access memory. A stacked gate is formed on a substrate. A lightly doped drain region and a lightly doped source region are formed in the substrate. A thin spacer is then formed on a sidewall of the stacked gate on the lightly doped source region only. However, this thin spacer does not completely cover the lightly doped source and drain regions, that is, portions of the light doped source and drain regions are exposed. A thick spacer is then formed on the other sidewall of the stacked gate on the lightly doped drain region only. Using both the thin and the thick spacers as a mask, an ion implantation is performed to form a heavily doped source region and a heavily doped drain region in the substrate. A self-aligned silicide step is performed to form a salicide layer on the stacked gate, the source and the drain regions.

    摘要翻译： 一种制造静态随机存取存储器的方法。 堆叠栅极形成在基板上。 在衬底中形成轻掺杂漏极区和轻掺杂源区。 然后，仅在轻掺杂源极区域上的层叠栅极的侧壁上形成薄的间隔物。 然而，这种薄的间隔物并不完全覆盖轻掺杂的源极和漏极区域，即，光掺杂源极和漏极区域的部分被暴露。 然后，仅在轻掺杂漏极区域上的层叠栅极的另一个侧壁上形成厚的间隔物。 使用薄的和厚的间隔物作为掩模，执行离子注入以在衬底中形成重掺杂的源极区域和重掺杂的漏极区域。 执行自对准的硅化物步骤以在堆叠的栅极，源极和漏极区域上形成自对准硅化物层。

    Method of manufacturing a shallow trench isolation structure
    3.
    发明授权
    Method of manufacturing a shallow trench isolation structure 失效
    制造浅沟槽隔离结构的方法

    公开(公告)号：US5918131A

    公开(公告)日：1999-06-29

    申请号：US961062

    申请日：1997-10-30

    申请人： Shih-Ying Hsu ,  Heng-Sheng Huang

    发明人： Shih-Ying Hsu ,  Heng-Sheng Huang

    IPC分类号： H01L21/762 ,  H01L21/336 ,  H01L21/76

    CPC分类号： H01L21/76232

    摘要： A method of manufacturing a shallow trench isolation structure that utilizes the early formation of a strong oxide spacers so that for any subsequent pad oxide layer or sacrificial oxide layer removal using a wet etching method, the oxide layer adjacent to the substrate will not be over-etched to form recesses, thereby preventing the lowering of threshold voltage and the induction of a kink effect. The method includes the steps of forming a mask over a substrate and then patterning the mask to form a protective layer for subsequent etching operation. An oxide space is farmed on the sidewalls of the mask over the surface of the substrate. Subsequently, a trench is formed in the substrate along the side edges of the oxide spacers. A liner oxide box is formed on the sidewall of the trend and the liner oxide layer does not fill the trench. This is followed by filling the trench with a second oxide layer. After planarizing the upper surface with a chemical-mechanical polishing action, the mask is removed.

    摘要翻译： 一种制造浅沟槽隔离结构的方法，其利用早期形成强氧化物间隔物，使得对于任何后续的衬垫氧化物层或使用湿蚀刻方法的牺牲氧化物层去除，与衬底相邻的氧化物层将不会过量， 蚀刻形成凹部，从而防止阈值电压的降低和扭结效应的诱导。 该方法包括以下步骤：在衬底上形成掩模，然后对掩模进行图案化以形成用于后续蚀刻操作的保护层。 掩模的侧壁上的氧化物空间被堆积在衬底的表面上。 随后，沿着氧化物间隔物的侧边缘在衬底中形成沟槽。 在趋势的侧壁上形成衬里氧化物盒，并且衬垫氧化物层不填充沟槽。 然后用第二氧化物层填充沟槽。 在用化学机械抛光作用对上表面进行平面化之后，去除掩模。

    Method for fabricating semiconductor devices with dual gate oxides
    9.
    发明授权
    Method for fabricating semiconductor devices with dual gate oxides 失效
    制造具有双栅氧化物的半导体器件的方法

    公开(公告)号：US06346445B1

    公开(公告)日：2002-02-12

    申请号：US09715826

    申请日：2000-11-17

    申请人： Shih-Ying Hsu

    发明人： Shih-Ying Hsu

    IPC分类号： H01L21336

    CPC分类号： H01L21/823481 ,  H01L21/76232 ,  H01L21/823462 ,  Y10S438/981

    摘要： A dual gate oxides' process for mixed-mode IC is provided. More particularly, the present invention relates to a dual gate oxides' process for mixed-mode IC, which protects and improves the dual gate oxides' quality.

    摘要翻译： 提供了混合模式IC的双栅氧化法。 更具体地说，本发明涉及一种用于混合模式IC的双栅极氧化物工艺，其保护和改善双栅极氧化物的质量。

    Method for forming twin gate CMOS
    10.
    发明授权
    Method for forming twin gate CMOS 失效
    双栅极CMOS的形成方法

    公开(公告)号：US06258643B1

    公开(公告)日：2001-07-10

    申请号：US09344691

    申请日：1999-06-25

    申请人： Shih-Ying Hsu

    发明人： Shih-Ying Hsu

    IPC分类号： H01L218238

    CPC分类号： H01L21/823842

    摘要： A method for forming an adapted small dimension and more quality fabrication is disclosed. In one embodiment, the present invention provides a twin gate CMOS, which includes isolations formed in a semiconductor substrate. A P-well and an N-well inside the semiconductor substrate are formed and isolated by an isolating region. Next, a gate oxide layer and a first polysilicon layer are formed sequentially above the P-well and an N-well. A polysilicon layer doped in-situ with N-type ions. Sequentially, a first oxide layer is deposited and a first photoresist layer is formed on the polysilicon layer above P-well region, wherein etching respective patterns on the first oxide layer and the polysilicon layer. An amorphous silicon layer doped with P-type ions by implanation is formed over the gate oxide layer and the first oxide layer above the semiconductor substrate. After forming a second oxide layer on the amorphous silicon layer. A SOG (spin-on glass) layer is deposited above the substrate, and then the SOG (spin-on glass) layer, major second oxide layer and a portion of amorphous silicon layer are removed until the first oxide layer is exposed by chemical mechanical polishing. Next, first etch bulgy P+-type amorphous silicon layer until the amorphous silicon layer surface is smooth, and then etch back the first dielectric layer and second dielectric layer. Finally, respectively forming a P+-type gate above the N-well and a N+-type gate on the P-well.

    摘要翻译： 公开了一种用于形成适应小尺寸和更高质量制造的方法。 在一个实施例中，本发明提供一种双栅极CMOS，其包括在半导体衬底中形成的隔离。 半导体衬底内部的P阱和N阱由隔离区形成并隔离。 接下来，在P阱和N阱上顺序地形成栅极氧化物层和第一多晶硅层。 用N型离子原位掺杂的多晶硅层。 顺序地，沉积第一氧化物层，并且在P阱区域上的多晶硅层上形成第一光致抗蚀剂层，其中蚀刻第一氧化物层和多晶硅层上的各个图案。 在栅极氧化物层和半导体衬底上方的第一氧化物层上形成通过注入掺杂P型离子的非晶硅层。 在非晶硅层上形成第二氧化物层之后。 在基板上方沉积SOG（旋涂玻璃）层，然后去除SOG（旋涂玻璃）层，主要第二氧化物层和非晶硅层的一部分，直到第一氧化物层通过化学机械 抛光。 接下来，首先蚀刻膨胀P +型非晶硅层，直到非晶硅层表面光滑，然后蚀刻第一介电层和第二介电层。 最后，在P阱上分别形成N阱上的P +型栅极和N +型栅极。