Abstract:
A computer platform memory access control method and system is proposed, which is designed for use with a computer platform, such as a network server, for providing the server with a memory access control function with a memory configuration automatic setting capability, which is characterized by the arrangement of a configuration data exchange path between a memory control chip and an I/O control chip on the server's motherboard, so as to allow a set of memory specification data stored in an I/O configuration register of the ICH I/O control chip to be mapped via the configuration data exchange path to a memory configuration register of the memory control chip, such that a memory access action can be performed based on the memory specification data mapped from the I/O control chip. This feature allows the operation and network management of servers to be made more efficient.
Abstract:
An apparatus and method are disclosed to implement a universal 3D (3-Dimensional) image system with automatic search for 3D communication protocol. The apparatus includes a memory to store a plurality of communication protocols. The apparatus further includes a controller operatively coupled to the memory to detect a transmitted communication protocol by comparing the transmitted communication protocol with the plurality of communication protocols stored in the memory of the glasses. In addition, the controller receives and processes the 3D image data based on the transmitted communication protocol.
Abstract:
A computer platform memory access control method and system is proposed, which is designed for use with a computer platform, such as a network server, for providing the server with a memory access control function with a memory configuration automatic setting capability, which is characterized by the arrangement of a configuration data exchange path between a memory control chip and an I/O control chip on the server's motherboard, so as to allow a set of memory specification data stored in an I/O configuration register of the ICH I/O control chip to be mapped via the configuration data exchange path to a memory configuration register of the memory control chip, such that a memory access action can be performed based on the memory specification data mapped from the I/O control chip. This feature allows the operation and network management of servers to be made more efficient.
Abstract:
A method for treating or preventing infarction of a patient comprising administering a hepsin antagonist with a dosage effective to suppress or inactivate hepsin's expression over a sustained period.
Abstract:
An immersion lithography system is disclosed to comprise a fluid containing feature for providing an immersion fluid for performing immersion lithography on a wafer, and a seal ring covering a predetermined portion of a wafer edge for preventing the immersion fluid from leaking through the covered portion of the wafer edge while the fluid is used for the immersion lithography.
Abstract:
Disclosed is an apparatus for quickly generating an error free MIB file of the type used by a SNMP manager to manage and display error and log trap messages received from agents reporting to said manager. This is accomplished by retrieving data from definition and template libraries to be used in conjunction with a network element database to correctly generate, element by element, a completed MIB file.
Abstract:
The present invention discloses pre-amplifier with a selectable threshold voltage in a decision feedback equalization circuit to reduce tap weight variation. A decision feedback equalization circuit includes a summer circuit and a pre-amplifier with an offset generator, wherein the pre-amplifier includes a pair of differential amplifiers and each biased by a respective current bias and each having first and second output nodes coupled to a supply voltage via a respective resistive element, R. The resistive elements may be implemented, for example, using diode-configured transistors, biased transistors, resistor, or any other active or passive circuitry for establishing a resistance. The inputs of first differential amplifier are coupled to the summer's output. The inputs of second differential amplifier are coupled to a reference voltage circuit that comprised of a resistive element and a respective current DAC (IDAC).
Abstract:
A programmable current mirror a reference transistor, first and second mirror transistors, and a first current bypass. The reference transistor has a source and a gate coupled to a reference current node. The first and second mirror transistors are coupled together in series at a first node. Each of the first and second mirror transistors having gates coupled to each other and to the gate of the reference transistor. The first current bypass including a switch disposed in parallel with the second mirror transistor. The first current bypass is coupled to a source and a drain of the second mirror transistor and to the first node.
Abstract:
A programmable current mirror a reference transistor, first and second mirror transistors, and a first current bypass. The reference transistor has a source and a gate coupled to a reference current node. The first and second mirror transistors are coupled together in series at a first node. Each of the first and second mirror transistors having gates coupled to each other and to the gate of the reference transistor. The first current bypass including a switch disposed in parallel with the second mirror transistor. The first current bypass is coupled to a source and a drain of the second mirror transistor and to the first node.