公开(公告)号：US20110081753A1

公开(公告)日：2011-04-07

申请号：US12896391

申请日：2010-10-01

申请人： Shinichi YAMANARI ,  Ryoichi Yoshifuku ,  Masaaki Shinohara ,  Takahiro Maruyama ,  Kenji Kawai ,  Yusaku Hirota

发明人： Shinichi YAMANARI ,  Ryoichi Yoshifuku ,  Masaaki Shinohara ,  Takahiro Maruyama ,  Kenji Kawai ,  Yusaku Hirota

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/31111 ,  H01L21/823462 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

摘要： A manufacturing method of a semiconductor device is provided for improving the reliability of a semiconductor device including a MISFET with a high dielectric constant gate insulator and a metal gate electrode. A first Hf-containing insulating film containing Hf, La, and O as a principal component is formed as a high dielectric constant gate insulator for an n-channel MISFET. A second Hf-containing insulating film containing Hf, Al, and O as a principal component is formed as a high dielectric constant gate insulator for a p-channel MISFET. Then, a metal film and a silicon film are formed and patterned by dry etching to thereby form first and second gate electrodes. Thereafter, parts of the first and second Hf-containing insulating films not covered with the first and second gate electrodes are removed by wet etching. At this time, a wet process with an acid solution not containing hydrofluoric acid, and another wet process with an alkaline solution are performed, and then a further wet process with an acid solution containing hydrofluoric acid is performed.

摘要翻译： 提供半导体器件的制造方法，用于提高包括具有高介电常数栅极绝缘体和金属栅电极的MISFET的半导体器件的可靠性。 作为主要成分，含有Hf，La，O的第一含Hf绝缘膜形成为n型MISFET的高介电常数栅极绝缘体。 作为主要成分，含有Hf，Al，O的第二含Hf绝缘膜形成为p型MI​​SFET的高介电常数栅极绝缘体。 然后，通过干蚀刻形成金属膜和硅膜并图案化，从而形成第一和第二栅电极。 此后，通过湿蚀刻除去未被第一和第二栅电极覆盖的第一和第二Hf含绝缘膜的部分。 此时，进行用不含氢氟酸的酸溶液的湿法和用碱性溶液的另一种湿法，然后进行用含有氢氟酸的酸溶液进一步的湿法。

公开(公告)号：US07537987B2

公开(公告)日：2009-05-26

申请号：US11551861

申请日：2006-10-23

申请人： Masahiko Higashi ,  Satoshi Kume ,  Jiro Yugami ,  Shinichi Yamanari ,  Takahiro Maruyama ,  Itaru Kanno

发明人： Masahiko Higashi ,  Satoshi Kume ,  Jiro Yugami ,  Shinichi Yamanari ,  Takahiro Maruyama ,  Itaru Kanno

IPC分类号： H01L21/84

CPC分类号： H01L21/32134 ,  H01L21/28079 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/4958

摘要： In a semiconductor device manufacturing method of the invention, a metal film, for forming a gate electrode, is formed on a gate insulating film. Subsequently, when the metal film is processed, part of the metal film is removed by a wet etching process using a given chemical liquid.

摘要翻译： 在本发明的半导体器件制造方法中，在栅极绝缘膜上形成用于形成栅电极的金属膜。 随后，当处理金属膜时，通过使用给定的化学液体的湿蚀刻工艺去除部分金属膜。

公开(公告)号：US20080308869A1

公开(公告)日：2008-12-18

申请号：US12194631

申请日：2008-08-20

申请人： Hidekazu ODA ,  Takahisa Eimori ,  Jiro Yugami ,  Takahiro Maruyama ,  Tomohiro Yamashita ,  Yukio Nishida ,  Shinichi Yamanari ,  Takashi Hayashi ,  Kenichi Mori

发明人： Hidekazu ODA ,  Takahisa Eimori ,  Jiro Yugami ,  Takahiro Maruyama ,  Tomohiro Yamashita ,  Yukio Nishida ,  Shinichi Yamanari ,  Takashi Hayashi ,  Kenichi Mori

IPC分类号： H01L29/00

CPC分类号： H01L21/823842

摘要： The technology which can control a threshold value appropriately, adopting the material which fitted each gate electrode of the MOS structure from which a threshold value differs without making the manufacturing process complicated, and does not make remarkable diffusion to the channel region from the gate electrode is offered.The PMOS transistor has a gate electrode GP, and an N type well which confronts each other via a gate insulating film with this, and the NMOS transistor has a gate electrode GN, and an P type well which confronts each other via a gate insulating film with this. While gate electrode GN includes a polycrystalline silicon layer, gate electrode GP is provided with the laminated structure of a metal layer/polycrystalline silicon layer.

摘要翻译： 可以适当地控制阈值的技术，采用在不使制造过程复杂的情况下使阈值相差不同的MOS结构的每个栅电极的装配材料，并且不会从栅电极向沟道区域显着扩散的技术是 提供。 PMOS晶体管具有栅电极GP和通过栅绝缘膜相互面对的N型阱，并且NMOS晶体管具有栅电极GN和通过栅极绝缘膜相互面对的P型阱 有了这个。 当栅电极GN包括多晶硅层时，栅电极GP具有金属层/多晶硅层的叠层结构。

公开(公告)号：US20070099406A1

公开(公告)日：2007-05-03

申请号：US11551861

申请日：2006-10-23

申请人： Masahiko Higashi ,  Satoshi Kume ,  Jiro Yugami ,  Shinichi Yamanari ,  Takahiro Maruyama ,  Itaru Kanno

发明人： Masahiko Higashi ,  Satoshi Kume ,  Jiro Yugami ,  Shinichi Yamanari ,  Takahiro Maruyama ,  Itaru Kanno

IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/336

CPC分类号： H01L21/32134 ,  H01L21/28079 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/4958

摘要： In a semiconductor device manufacturing method of the invention, a metal film, for forming a gate electrode, is formed on a gate insulating film. Subsequently, when the metal film is processed, part of the metal film is removed by a wet etching process using a given chemical liquid.

摘要翻译： 在本发明的半导体器件制造方法中，在栅极绝缘膜上形成用于形成栅电极的金属膜。 随后，当处理金属膜时，通过使用给定的化学液体的湿蚀刻工艺去除部分金属膜。

公开(公告)号：US20070007602A1

公开(公告)日：2007-01-11

申请号：US11478669

申请日：2006-07-03

申请人： Hidekazu Oda ,  Takahisa Eimori ,  Jiro Yugami ,  Takahiro Maruyama ,  Tomohiro Yamashita ,  Yukio Nishida ,  Shinichi Yamanari ,  Takashi Hayashi ,  Kenichi Mori

发明人： Hidekazu Oda ,  Takahisa Eimori ,  Jiro Yugami ,  Takahiro Maruyama ,  Tomohiro Yamashita ,  Yukio Nishida ,  Shinichi Yamanari ,  Takashi Hayashi ,  Kenichi Mori

IPC分类号： H01L29/94

CPC分类号： H01L21/823842

摘要： The technology which can control a threshold value appropriately, adopting the material which fitted each gate electrode of the MOS structure from which a threshold value differs without making the manufacturing process complicated, and does not make remarkable diffusion to the channel region from the gate electrode is offered. The PMOS transistor has a gate electrode GP, and an N type well which confronts each other via a gate insulating film with this, and the NMOS transistor has a gate electrode GN, and an P type well which confronts each other via a gate insulating film with this. While gate electrode GN includes a polycrystalline silicon layer, gate electrode GP is provided with the laminated structure of a metal layer/polycrystalline silicon layer.

摘要翻译： 可以适当地控制阈值的技术，采用在不使制造过程复杂的情况下使阈值相差不同的MOS结构的每个栅电极的装配材料，并且不会从栅电极向沟道区域显着扩散的技术是 提供。 PMOS晶体管具有栅电极GP和通过栅绝缘膜相互面对的N型阱，并且NMOS晶体管具有栅电极GN和通过栅极绝缘膜相互面对的P型阱 有了这个。 当栅电极GN包括多晶硅层时，栅电极GP具有金属层/多晶硅层的叠层结构。

公开(公告)号：US07989283B2

公开(公告)日：2011-08-02

申请号：US12896391

申请日：2010-10-01

申请人： Shinichi Yamanari ,  Ryoichi Yoshifuku ,  Masaaki Shinohara ,  Takahiro Maruyama ,  Kenji Kawai ,  Yusaku Hirota

发明人： Shinichi Yamanari ,  Ryoichi Yoshifuku ,  Masaaki Shinohara ,  Takahiro Maruyama ,  Kenji Kawai ,  Yusaku Hirota

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/31111 ,  H01L21/823462 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/6659 ,  H01L29/7833

摘要： A manufacturing method of a semiconductor device is provided for improving the reliability of a semiconductor device including a MISFET with a high dielectric constant gate insulator and a metal gate electrode. A first Hf-containing insulating film containing Hf, La, and O as a principal component is formed as a high dielectric constant gate insulator for an n-channel MISFET. A second Hf-containing insulating film containing Hf, Al, and O as a principal component is formed as a high dielectric constant gate insulator for a p-channel MISFET. Then, a metal film and a silicon film are formed and patterned by dry etching to thereby form first and second gate electrodes. Thereafter, parts of the first and second Hf-containing insulating films not covered with the first and second gate electrodes are removed by wet etching. At this time, a wet process with an acid solution not containing hydrofluoric acid, and another wet process with an alkaline solution are performed, and then a further wet process with an acid solution containing hydrofluoric acid is performed.

摘要翻译： 提供半导体器件的制造方法，用于提高包括具有高介电常数栅极绝缘体和金属栅电极的MISFET的半导体器件的可靠性。 作为主要成分，含有Hf，La，O的第一含Hf绝缘膜形成为n型MISFET的高介电常数栅极绝缘体。 作为主要成分，含有Hf，Al，O的第二含Hf绝缘膜形成为p型MI​​SFET的高介电常数栅极绝缘体。 然后，通过干蚀刻形成金属膜和硅膜并图案化，从而形成第一和第二栅电极。 此后，通过湿蚀刻除去未被第一和第二栅电极覆盖的第一和第二Hf含绝缘膜的部分。 此时，进行用不含氢氟酸的酸溶液的湿法和用碱性溶液的另一种湿法，然后进行用含有氢氟酸的酸溶液进一步的湿法。