公开(公告)号：US20080308869A1

公开(公告)日：2008-12-18

申请号：US12194631

申请日：2008-08-20

申请人： Hidekazu ODA ,  Takahisa Eimori ,  Jiro Yugami ,  Takahiro Maruyama ,  Tomohiro Yamashita ,  Yukio Nishida ,  Shinichi Yamanari ,  Takashi Hayashi ,  Kenichi Mori

发明人： Hidekazu ODA ,  Takahisa Eimori ,  Jiro Yugami ,  Takahiro Maruyama ,  Tomohiro Yamashita ,  Yukio Nishida ,  Shinichi Yamanari ,  Takashi Hayashi ,  Kenichi Mori

IPC分类号： H01L29/00

CPC分类号： H01L21/823842

摘要： The technology which can control a threshold value appropriately, adopting the material which fitted each gate electrode of the MOS structure from which a threshold value differs without making the manufacturing process complicated, and does not make remarkable diffusion to the channel region from the gate electrode is offered.The PMOS transistor has a gate electrode GP, and an N type well which confronts each other via a gate insulating film with this, and the NMOS transistor has a gate electrode GN, and an P type well which confronts each other via a gate insulating film with this. While gate electrode GN includes a polycrystalline silicon layer, gate electrode GP is provided with the laminated structure of a metal layer/polycrystalline silicon layer.

摘要翻译： 可以适当地控制阈值的技术，采用在不使制造过程复杂的情况下使阈值相差不同的MOS结构的每个栅电极的装配材料，并且不会从栅电极向沟道区域显着扩散的技术是 提供。 PMOS晶体管具有栅电极GP和通过栅绝缘膜相互面对的N型阱，并且NMOS晶体管具有栅电极GN和通过栅极绝缘膜相互面对的P型阱 有了这个。 当栅电极GN包括多晶硅层时，栅电极GP具有金属层/多晶硅层的叠层结构。

公开(公告)号：US20070007602A1

公开(公告)日：2007-01-11

申请号：US11478669

申请日：2006-07-03

申请人： Hidekazu Oda ,  Takahisa Eimori ,  Jiro Yugami ,  Takahiro Maruyama ,  Tomohiro Yamashita ,  Yukio Nishida ,  Shinichi Yamanari ,  Takashi Hayashi ,  Kenichi Mori

发明人： Hidekazu Oda ,  Takahisa Eimori ,  Jiro Yugami ,  Takahiro Maruyama ,  Tomohiro Yamashita ,  Yukio Nishida ,  Shinichi Yamanari ,  Takashi Hayashi ,  Kenichi Mori

IPC分类号： H01L29/94

CPC分类号： H01L21/823842

摘要： The technology which can control a threshold value appropriately, adopting the material which fitted each gate electrode of the MOS structure from which a threshold value differs without making the manufacturing process complicated, and does not make remarkable diffusion to the channel region from the gate electrode is offered. The PMOS transistor has a gate electrode GP, and an N type well which confronts each other via a gate insulating film with this, and the NMOS transistor has a gate electrode GN, and an P type well which confronts each other via a gate insulating film with this. While gate electrode GN includes a polycrystalline silicon layer, gate electrode GP is provided with the laminated structure of a metal layer/polycrystalline silicon layer.

摘要翻译： 可以适当地控制阈值的技术，采用在不使制造过程复杂的情况下使阈值相差不同的MOS结构的每个栅电极的装配材料，并且不会从栅电极向沟道区域显着扩散的技术是 提供。 PMOS晶体管具有栅电极GP和通过栅绝缘膜相互面对的N型阱，并且NMOS晶体管具有栅电极GN和通过栅极绝缘膜相互面对的P型阱 有了这个。 当栅电极GN包括多晶硅层时，栅电极GP具有金属层/多晶硅层的叠层结构。

公开(公告)号：US07537987B2

公开(公告)日：2009-05-26

申请号：US11551861

申请日：2006-10-23

申请人： Masahiko Higashi ,  Satoshi Kume ,  Jiro Yugami ,  Shinichi Yamanari ,  Takahiro Maruyama ,  Itaru Kanno

发明人： Masahiko Higashi ,  Satoshi Kume ,  Jiro Yugami ,  Shinichi Yamanari ,  Takahiro Maruyama ,  Itaru Kanno

IPC分类号： H01L21/84

CPC分类号： H01L21/32134 ,  H01L21/28079 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/4958

摘要： In a semiconductor device manufacturing method of the invention, a metal film, for forming a gate electrode, is formed on a gate insulating film. Subsequently, when the metal film is processed, part of the metal film is removed by a wet etching process using a given chemical liquid.

摘要翻译： 在本发明的半导体器件制造方法中，在栅极绝缘膜上形成用于形成栅电极的金属膜。 随后，当处理金属膜时，通过使用给定的化学液体的湿蚀刻工艺去除部分金属膜。

公开(公告)号：US20070099406A1

公开(公告)日：2007-05-03

申请号：US11551861

申请日：2006-10-23

申请人： Masahiko Higashi ,  Satoshi Kume ,  Jiro Yugami ,  Shinichi Yamanari ,  Takahiro Maruyama ,  Itaru Kanno

发明人： Masahiko Higashi ,  Satoshi Kume ,  Jiro Yugami ,  Shinichi Yamanari ,  Takahiro Maruyama ,  Itaru Kanno

IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/336

CPC分类号： H01L21/32134 ,  H01L21/28079 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/4958

摘要： In a semiconductor device manufacturing method of the invention, a metal film, for forming a gate electrode, is formed on a gate insulating film. Subsequently, when the metal film is processed, part of the metal film is removed by a wet etching process using a given chemical liquid.

摘要翻译： 在本发明的半导体器件制造方法中，在栅极绝缘膜上形成用于形成栅电极的金属膜。 随后，当处理金属膜时，通过使用给定的化学液体的湿蚀刻工艺去除部分金属膜。

公开(公告)号：US20100102395A1

公开(公告)日：2010-04-29

申请号：US12572646

申请日：2009-10-02

申请人： Yoshiki Yamamoto ,  Yukio Nishida ,  Jiro Yugami

发明人： Yoshiki Yamamoto ,  Yukio Nishida ,  Jiro Yugami

IPC分类号： H01L27/092 ,  H01L21/28 ,  H01L21/8238

CPC分类号： H01L21/823828 ,  H01L21/823857

摘要： Provided is a semiconductor device capable of having a single metal/dual high-k structure with a good shape and having flat band voltages suited for nMOS and pMOS, respectively. The semiconductor device according to the one embodiment of the present invention has a first conductivity type MOSFET and a second conductivity type MOSFET. The first and second conductivity type MOSFETs are each equipped with a first insulating film formed over a semiconductor substrate, a second insulating film formed over the first insulating film and made of an insulating material having a higher dielectric constant than the first insulating film, and a gate electrode formed over the second insulating film and having, as a lower layer of the gate electrode, a metal layer containing a material which diffuses into the second insulating film to control a work function thereof. The second conductivity type MOSFET is equipped further with a diffusion barrier film formed between the first insulating film and the second insulating film to prevent diffusion of a work-function controlling material into the interface of the first insulating film.

摘要翻译： 提供了能够分别具有适合于nMOS和pMOS的具有良好形状并具有平坦带电压的单个金属/双高k结构的半导体器件。 根据本发明的一个实施例的半导体器件具有第一导电型MOSFET和第二导电型MOSFET。 第一导电型MOSFET和第二导电型MOSFET分别配置有形成在半导体基板上的第一绝缘膜，形成在第一绝缘膜上并且由具有比第一绝缘膜高的介电常数的绝缘材料制成的第二绝缘膜， 栅电极形成在第二绝缘膜上，并且具有作为栅电极的下层的含有扩散到第二绝缘膜中以控制其功函的材料的金属层。 第二导电型MOSFET还具有形成在第一绝缘膜和第二绝缘膜之间的扩散阻挡膜，以防止功函数控制材料扩散到第一绝缘膜的界面中。

公开(公告)号：US08796780B2

公开(公告)日：2014-08-05

申请号：US12572646

申请日：2009-10-02

申请人： Yoshiki Yamamoto ,  Yukio Nishida ,  Jiro Yugami

发明人： Yoshiki Yamamoto ,  Yukio Nishida ,  Jiro Yugami

IPC分类号： H01L29/72

CPC分类号： H01L21/823828 ,  H01L21/823857

摘要： Provided is a semiconductor device capable of having a single metal/dual high-k structure with a good shape and having flat band voltages suited for nMOS and pMOS, respectively. The semiconductor device according to the one embodiment of the present invention has a first conductivity type MOSFET and a second conductivity type MOSFET. The first and second conductivity type MOSFETs are each equipped with a first insulating film formed over a semiconductor substrate, a second insulating film formed over the first insulating film and made of an insulating material having a higher dielectric constant than the first insulating film, and a gate electrode formed over the second insulating film and having, as a lower layer of the gate electrode, a metal layer containing a material which diffuses into the second insulating film to control a work function thereof. The second conductivity type MOSFET is equipped further with a diffusion barrier film formed between the first insulating film and the second insulating film to prevent diffusion of a work-function controlling material into the interface of the first insulating film.

摘要翻译： 提供了能够分别具有适合于nMOS和pMOS的具有良好形状并具有平坦带电压的单个金属/双高k结构的半导体器件。 根据本发明的一个实施例的半导体器件具有第一导电型MOSFET和第二导电型MOSFET。 第一导电型MOSFET和第二导电型MOSFET分别配置有形成在半导体基板上的第一绝缘膜，形成在第一绝缘膜上并且由具有比第一绝缘膜高的介电常数的绝缘材料制成的第二绝缘膜，以及 栅电极形成在第二绝缘膜上，并且具有作为栅电极的下层的含有扩散到第二绝缘膜中以控制其功函的材料的金属层。 第二导电型MOSFET还具有形成在第一绝缘膜和第二绝缘膜之间的扩散阻挡膜，以防止功函数控制材料扩散到第一绝缘膜的界面中。

公开(公告)号：US07741201B2

公开(公告)日：2010-06-22

申请号：US11371082

申请日：2006-03-09

申请人： Jiro Yugami ,  Masao Inoue ,  Kenichi Mori ,  Shinsuke Sakashita

发明人： Jiro Yugami ,  Masao Inoue ,  Kenichi Mori ,  Shinsuke Sakashita

IPC分类号： H01L21/3205

CPC分类号： H01L29/495 ,  H01L21/28176 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66575

摘要： The semiconductor device includes a semiconductor substrate, a gate insulating film formed in contact with an upper side of the semiconductor substrate, and a gate electrode formed on the upper side of the gate insulating film and made of metal nitride or metal nitride silicide. A buffer layer for preventing diffusion of nitrogen and silicon is interposed between the gate insulating film and the gate electrode. Preferably, the buffer layer has a thickness of 5 nm or less. In the case where gate electrode contains Ti elements, and the gate insulating film contains Hf elements, the buffer layer preferably contains a titanium film.

摘要翻译： 半导体器件包括半导体衬底，与半导体衬底的上侧接触形成的栅极绝缘膜，以及形成在栅极绝缘膜的上侧并由金属氮化物或金属氮化物硅化物制成的栅电极。 用于防止氮和硅扩散的缓冲层插入在栅极绝缘膜和栅电极之间。 优选地，缓冲层的厚度为5nm以下。 在栅极含有Ti元素，栅极绝缘膜含有Hf元素的情况下，缓冲层优选含有钛膜。

公开(公告)号：US20060214245A1

公开(公告)日：2006-09-28

申请号：US11371082

申请日：2006-03-09

申请人： Jiro Yugami ,  Masao Inoue ,  Kenichi Mori ,  Shinsuke Sakashita

发明人： Jiro Yugami ,  Masao Inoue ,  Kenichi Mori ,  Shinsuke Sakashita

IPC分类号： H01L29/94

CPC分类号： H01L29/495 ,  H01L21/28176 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66575

摘要： The semiconductor device includes a semiconductor substrate, a gate insulating film formed in contact with an upper side of the semiconductor substrate, and a gate electrode formed on the upper side of the gate insulating film and made of metal nitride or metal nitride silicide. A buffer layer for preventing diffusion of nitrogen and silicon is interposed between the gate insulating film and the gate electrode. Preferably, the buffer layer has a thickness of 5 nm or less. In the case where gate electrode contains Ti elements, and the gate insulating film contains Hf elements, the buffer layer preferably contains a titanium film.

摘要翻译： 半导体器件包括半导体衬底，与半导体衬底的上侧接触形成的栅极绝缘膜，以及形成在栅极绝缘膜的上侧并由金属氮化物或金属氮化物硅化物制成的栅电极。 用于防止氮和硅扩散的缓冲层插入在栅极绝缘膜和栅电极之间。 优选地，缓冲层的厚度为5nm以下。 在栅极含有Ti元素，栅极绝缘膜含有Hf元素的情况下，缓冲层优选含有钛膜。

公开(公告)号：US08552507B2

公开(公告)日：2013-10-08

申请号：US13515500

申请日：2009-12-24

申请人： Jiro Yugami

发明人： Jiro Yugami

IPC分类号： H01L21/70

CPC分类号： H01L21/823857 ,  H01L21/28194 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A p-type MIS transistor Qp arranged in a pMIS region Rp of a silicon substrate 1 includes a pMIS gate electrode GEp formed so as to interpose a pMIS gate insulating film GIp formed of a first insulating film z1 and a first high-dielectric film hk1, and an n-type MIS transistor Qn arranged in an nMIS region Rn includes an nMIS gate electrode GEn formed so as to interpose an nMIS gate insulating film GIn formed of a first insulating film z1 and a second high-dielectric film hk2. The first high-dielectric film hk1 is formed of an insulating film mainly made of hafnium and oxygen with containing aluminum, titanium, or tantalum. Also, the second high-dielectric film hk2 is formed of an insulating film mainly made of hafnium, silicon, and oxygen with containing an element of any of group Ia, group IIa, and group IIIa.

摘要翻译： 布置在硅衬底1的pMIS区域Rp中的p型MIS晶体管Qp包括pMIS栅极电极GEp，其形成为将由第一绝缘膜z1和第一高介电膜hk1形成的pMIS栅极绝缘膜GIp ，并且配置在nMIS区域Rn中的n型MIS晶体管Qn包括形成为以由第一绝缘膜z1和第二高介电膜hk2形成的nMIS栅极绝缘膜GIn形成的nMIS栅电极GEn。 第一高电介质膜hk1由主要由铪和含有铝，钛或钽的氧构成的绝缘膜形成。 此外，第二高电介质膜hk2由主要由铪，硅和氧制成的绝缘膜形成，其含有Ia，IIa和IIIa族中任一种的元素。

公开(公告)号：US07863125B2

公开(公告)日：2011-01-04

申请号：US12492648

申请日：2009-06-26

申请人： Shimpei Tsujikawa ,  Yasuhiko Akamatsu ,  Hiroshi Umeda ,  Jiro Yugami ,  Masaharu Mizutani ,  Masao Inoue ,  Junichi Tsuchimoto ,  Kouji Nomura

发明人： Shimpei Tsujikawa ,  Yasuhiko Akamatsu ,  Hiroshi Umeda ,  Jiro Yugami ,  Masaharu Mizutani ,  Masao Inoue ,  Junichi Tsuchimoto ,  Kouji Nomura

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857

摘要： The manufacturing method of the CMOS type semiconductor device which can suppress the boron penetration from the gate electrode of the pMOS transistors to the semiconductor substrate in the case that boron is contained in the gate electrodes, while enabling the improvement in the NBTI lifetime of the pMOS transistors, without degrading the performance of the nMOS transistors, is offered. The manufacturing method of the CMOS type semiconductor device concerning the present invention has the following process steps. Halogen is introduced to the semiconductor substrate of pMOS transistor formation areas. Next, a gate insulating film is formed on the semiconductor substrate of the pMOS transistor formation areas. Next, nitrogen is introduced to the gate insulating film.

摘要翻译： 在这种CMOS型半导体器件的制造方法中，能够抑制在栅极电极中含有硼的情况下，从pMOS晶体管的栅电极到半导体衬底的硼渗透，同时能够提高pMOS的NBTI寿命 提供了晶体管，而不降低nMOS晶体管的性能。 关于本发明的CMOS型半导体器件的制造方法具有以下工序。 卤素引入pMOS晶体管形成区域的半导体衬底。 接下来，在pMOS晶体管形成区域的半导体衬底上形成栅极绝缘膜。 接下来，将氮引入到栅极绝缘膜。