公开(公告)号：US09159687B2

公开(公告)日：2015-10-13

申请号：US13572302

申请日：2012-08-10

Applicant: Jung-Hua Chang ,  Cheng-Lin Huang ,  Jing-Cheng Lin

Inventor： Jung-Hua Chang ,  Cheng-Lin Huang ,  Jing-Cheng Lin

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L24/13 ,  H01L23/49816 ,  H01L24/11 ,  H01L2224/118 ,  H01L2224/13 ,  H01L2224/13016 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/06 ,  H01L2924/0665 ,  H01L2924/15788 ,  H01L2924/37001 ,  H01L2924/00

Abstract: A solder bump structure for a ball grid array (BGA) includes at least one under bump metal (UBM) layer and a solder bump formed over the at least one UBM layer. The solder bump has a bump width and a bump height and the ratio of the bump height over the bump width is less than 1.

Abstract translation: 用于球栅阵列（BGA）的焊料凸块结构包括在至少一个UBM层上形成的至少一个下凸块金属（UBM）层和焊料凸块。 焊料凸块具有凸块宽度和凸块高度，并且凸块高度比凸块宽度的比值小于1。

公开(公告)号：US08922004B2

公开(公告)日：2014-12-30

申请号：US12846260

申请日：2010-07-29

Applicant: Jing-Cheng Lin ,  Ya-Hsi Hwung ,  Hsin-Yu Chen ,  Po-Hao Tsai ,  Yan-Fu Lin ,  Cheng-Lin Huang ,  Fang Wen Tsai ,  Wen-Chih Chiou

Inventor： Jing-Cheng Lin ,  Ya-Hsi Hwung ,  Hsin-Yu Chen ,  Po-Hao Tsai ,  Yan-Fu Lin ,  Cheng-Lin Huang ,  Fang Wen Tsai ,  Wen-Chih Chiou

IPC: H01L23/48 ,  H01L23/488 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L24/11 ,  H01L23/488 ,  H01L24/13 ,  H01L24/16 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05099 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/10126 ,  H01L2224/10145 ,  H01L2224/1182 ,  H01L2224/11823 ,  H01L2224/1191 ,  H01L2224/13017 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13118 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13157 ,  H01L2224/13164 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/1357 ,  H01L2224/13578 ,  H01L2224/13583 ,  H01L2224/13644 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/1369 ,  H01L2224/16058 ,  H01L2224/16148 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/00011 ,  H01L2924/0002 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/37001 ,  H01L2924/00 ,  H01L2224/81 ,  H01L2224/16225 ,  H01L2924/00012 ,  H01L2224/16145 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2224/05552 ,  H01L2224/81805

Abstract: A work piece includes a copper bump having a top surface and sidewalls. A protection layer is formed on the sidewalls, and not on the top surface, of the copper bump. The protection layer includes a compound of copper and a polymer, and is a dielectric layer.

Abstract translation: 工件包括具有顶表面和侧壁的铜凸块。 在铜凸块的侧壁而不是顶表面上形成保护层。 保护层包括铜和聚合物的化合物，并且是介电层。

公开(公告)号：US08698308B2

公开(公告)日：2014-04-15

申请号：US13362913

申请日：2012-01-31

Applicant: Jing-Cheng Lin ,  Cheng-Lin Huang

Inventor： Jing-Cheng Lin ,  Cheng-Lin Huang

IPC: H01L29/40

CPC classification number: H01L24/16 ,  H01L21/56 ,  H01L21/563 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49816 ,  H01L23/49894 ,  H01L24/02 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0239 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05572 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11849 ,  H01L2224/13005 ,  H01L2224/13012 ,  H01L2224/13023 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81011 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/8191 ,  H01L2224/81911 ,  H01L2224/83104 ,  H01L2224/83855 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01079 ,  H01L2924/01028 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00014

Abstract: The mechanisms for forming bump structures enable forming bump structures between a chip and a substrate eliminating or reducing the risk of solder shorting, flux residue and voids in underfill. A lower limit can be established for a α ratio, defined by dividing the total height of copper posts in a bonded bump structure divided by the standoff of the bonded bump structure, to avoid shorting. A lower limit may also be established for standoff the chip package to avoid flux residue and underfill void formation. Further, aspect ratio of a copper post bump has a lower limit to avoid insufficient standoff and a higher limit due to manufacturing process limitation. By following proper bump design and process guidelines, yield and reliability of chip packages may be increases.

Abstract translation: 用于形成凸块结构的机构能够在芯片和基板之间形成凸块结构，消除或降低焊料短路，焊剂残留物和底部填充物中的空隙的风险。 可以通过将粘合凸块结构中的铜柱的总高度除以接合的凸块结构的间隙来限定的α比来限定下限，以避免短路。 也可以建立一个下限以排除芯片封装以避免焊剂残留和底部填充空隙形成。 此外，由于制造工艺限制，铜柱凸起的纵横比具有下限以避免不足的间隙和更高的极限。 通过遵循适当的凸块设计和工艺指南，芯片封装的产量和可靠性可能会增加。

公开(公告)号：US20130233601A1

公开(公告)日：2013-09-12

申请号：US13412958

申请日：2012-03-06

Applicant: Chin-Fu KAO ,  Wen-Chih Chiou ,  Jing-Cheng Lin ,  Cheng-Lin Huang ,  Po-Hao Tsai

Inventor： Chin-Fu KAO ,  Wen-Chih Chiou ,  Jing-Cheng Lin ,  Cheng-Lin Huang ,  Po-Hao Tsai

IPC: H05K1/09 ,  H05K1/00

CPC classification number: H01L24/14 ,  H01L22/32 ,  H01L23/3192 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05082 ,  H01L2224/05083 ,  H01L2224/05147 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/141 ,  H01L2224/14515 ,  H01L2224/81191 ,  H01L2224/81192 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/014

Abstract: A surface metal wiring structure for a substrate includes one or more functional μbumps formed of a first metal and an electrical test pad formed of a second metal for receiving an electrical test probe and electrically connected to the one or more functional μbumps. The surface metal wiring structure also includes a plurality of sacrificial μbumps formed of the first metal that are electrically connected to the electrical test pads, where the sacrificial μbumps are positioned closer to the electrical test pad than the one or more functional μbumps.

Abstract translation: 用于基板的表面金属布线结构包括由第一金属形成的一个或多个功能性微片和由用于接收电测试探针的第二金属形成的电测试焊盘，并电连接到所述一个或多个功能性微波。 表面金属布线结构还包括多个由第一金属形成的牺牲片，其电连接到电测试焊盘，其中牺牲微片比一个或多个功能性微片更靠近电测试垫定位。

公开(公告)号：US20130119382A1

公开(公告)日：2013-05-16

申请号：US13297845

申请日：2011-11-16

Applicant: Chin-Fu Kao ,  Cheng-Lin Huang ,  Jing-Cheng Lin

Inventor： Chin-Fu Kao ,  Cheng-Lin Huang ,  Jing-Cheng Lin

IPC: H01L23/544 ,  H01L21/28

CPC classification number: H01L22/32

Abstract: A system and method for plating a contact is provided. An embodiment comprises forming protective layers over a contact and a test pad, and then selectively removing the protective layer over the contact without removing the protective layer over the test pad. With the protective layer still on the test pad, a conductive layer may be plated onto the contact without plating it onto the test pad. After the contact has been plated, the protective layer over the contact may be removed.

Abstract translation: 提供了一种用于电镀触点的系统和方法。 一个实施例包括在触点和测试垫上形成保护层，然后在触头上选择性地去除保护层，而不需要在测试垫上移除保护层。 在保护层仍在测试焊盘上的情况下，可以将导电层电镀到触点上，而不将其覆盖在测试焊盘上。 接触电镀后，触点上的保护层可以被去除。

公开(公告)号：US08426307B2

公开(公告)日：2013-04-23

申请号：US13036599

申请日：2011-02-28

Applicant: Cheng-Lin Huang

Inventor： Cheng-Lin Huang

IPC: H01L21/4763

CPC classification number: H01L21/76834 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76849 ,  H01L21/76856

Abstract: An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, an oxide-based barrier layer directly on sidewalls of the opening, and conductive materials filling the remaining portion of the opening.

Abstract translation: 提供了具有改进的电阻率的集成电路结构及其形成方法。 集成电路结构包括电介质层，电介质层中的开口，直接位于开口侧壁上的基于氧化物的阻挡层，以及填充开口的剩余部分的导电材料。

公开(公告)号：US20120322261A1

公开(公告)日：2012-12-20

申请号：US13595835

申请日：2012-08-27

Applicant: Shau-Lin Shue ,  Cheng-Lin Huang ,  Ching-Hua Hsieh

Inventor： Shau-Lin Shue ,  Cheng-Lin Huang ,  Ching-Hua Hsieh

IPC: H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods for forming a via structure are provided. The method includes depositing a first-layer conductive line over a semiconductor substrate, forming a dielectric layer over the first-layer conductive line, forming a via opening in the dielectric layer and exposing the first-layer conductive line in the via opening, forming a recess portion in the first-layer conductive line, and filling the via opening to form a via extending through the dielectric layer to the first-layer conductive line. The via has a substantially tapered profile and substantially extends into the recess in the first-layer conductive line.

Abstract translation: 提供了形成通孔结构的方法。 该方法包括在半导体衬底上沉积第一层导电线，在第一层导电线上形成电介质层，在电介质层中形成通孔，并在通路孔中露出第一层导电线，形成 在第一层导电线中的凹陷部分，并且填充通孔开口以形成延伸通过介电层到第一层导电线的通孔。 通孔具有基本上锥形的轮廓并且基本上延伸到第一层导电线中的凹部中。

公开(公告)号：US20120306073A1

公开(公告)日：2012-12-06

申请号：US13343582

申请日：2012-01-04

Applicant: Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Cheng-Chieh Hsieh ,  Kuo-Ching Hsu ,  Ying-Ching Shih ,  Po-Hoa Tsai ,  Chin-Fu Kao ,  Cheng-Lin Huang ,  Jing-Cheng Lin

Inventor： Chen-Hua Yu ,  Shin-Puu Jeng ,  Shang-Yun Hou ,  Cheng-Chieh Hsieh ,  Kuo-Ching Hsu ,  Ying-Ching Shih ,  Po-Hoa Tsai ,  Chin-Fu Kao ,  Cheng-Lin Huang ,  Jing-Cheng Lin

IPC: H01L23/485 ,  H01L21/768

CPC classification number: H01L24/11 ,  H01L23/147 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L25/04 ,  H01L25/50 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05073 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05184 ,  H01L2224/05666 ,  H01L2224/05681 ,  H01L2224/05686 ,  H01L2224/10145 ,  H01L2224/10156 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/1182 ,  H01L2224/11831 ,  H01L2224/13017 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/13565 ,  H01L2224/13578 ,  H01L2224/13686 ,  H01L2224/16058 ,  H01L2224/16145 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/3651 ,  H01L2924/3841 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2924/049 ,  H01L2924/053 ,  H01L2924/00

Abstract: A device includes a top dielectric layer having a top surface. A metal pillar has a portion over the top surface of the top dielectric layer. A non-wetting layer is formed on a sidewall of the metal pillar, wherein the non-wetting layer is not wettable to the molten solder. A solder region is disposed over and electrically coupled to the metal pillar.

Abstract translation: 一种器件包括具有顶表面的顶部电介质层。 金属柱在顶部介电层的顶表面上具有一部分。 在金属柱的侧壁上形成非润湿层，其中非润湿层不能熔化到熔融焊料上。 焊接区域设置在金属柱上并电耦合到金属柱。

公开(公告)号：US08264086B2

公开(公告)日：2012-09-11

申请号：US11294217

申请日：2005-12-05

Applicant: Shau-Lin Shue ,  Cheng-Lin Huang ,  Ching-Hua Hsieh

Inventor： Shau-Lin Shue ,  Cheng-Lin Huang ,  Ching-Hua Hsieh

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L23/5226 ,  H01L21/76804 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A via structure having improved reliability and performance and methods of forming the same are provided. The via structure includes a first-layer conductive line, a second-layer conductive line, and a via electrically coupled between the first-layer conductive line and the second-layer conductive line. The via has a substantially tapered profile and substantially extends into a recess in the first-layer conductive line.

Abstract translation: 提供了具有改进的可靠性和性能的通孔结构及其形成方法。 通孔结构包括第一层导电线，第二层导电线和电耦合在第一层导电线和第二层导电线之间的通路。 通孔具有基本上锥形的轮廓并且基本上延伸到第一层导电线中的凹部中。

公开(公告)号：US07919862B2

公开(公告)日：2011-04-05

申请号：US11429879

申请日：2006-05-08

Applicant: Cheng-Lin Huang

Inventor： Cheng-Lin Huang

IPC: H01L23/52

CPC classification number: H01L21/76834 ,  H01L21/76831

Abstract: An integrated circuit structure having improved resistivity and a method for forming the same are provided. The integrated circuit structure includes a dielectric layer, an opening in the dielectric layer, an oxide-based barrier layer directly on sidewalls of the opening, and conductive materials filling the remaining portion of the opening.

Abstract translation: 提供了具有改进的电阻率的集成电路结构及其形成方法。 集成电路结构包括电介质层，电介质层中的开口，直接位于开口侧壁上的基于氧化物的阻挡层，以及填充开口的剩余部分的导电材料。