公开(公告)号：US07038951B2

公开(公告)日：2006-05-02

申请号：US10866442

申请日：2004-06-10

申请人： Yasuaki Hirano ,  Shuichiro Kouchi

发明人： Yasuaki Hirano ,  Shuichiro Kouchi

IPC分类号： G11C16/04

CPC分类号： G11C16/3477 ,  G11C16/16 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3468

摘要： A non-volatile semiconductor memory device includes a memory cell array including a plurality of memory cells, wherein information is writable to each of the plurality of memory cells and information is erasable from each of the plurality of memory cells, and the plurality of memory cells are grouped into at least one memory block; and a write and erasing section for performing a program write operation to a prescribed memory cell in one memory block in a prescribed voltage condition and for performing an erasing operation with respect to the memory cells in the one memory block, wherein the write and erasing section performs a pre-erasing write operation to the memory cells in the one memory block in a voltage condition, which is different from the prescribed voltage condition, before the erasing operation is performed with respect to the memory cells in the one memory block.

摘要翻译： 非挥发性半导体存储器件包括存储单元阵列，该存储单元阵列包括多个存储单元，其中信息可写入多个存储单元中的每一个，并且信息可从多个存储单元中的每一个擦除，并且多个存储单元 被分组成至少一个存储块; 以及写入和擦除部分，用于以规定的电压条件对一个存储器块中的规定的存储器单元执行程序写入操作，并且对于所述一个存储器块中的存储器单元执行擦除操作，其中写入和擦除部分 在相对于一个存储块中的存储单元执行擦除操作之前，在与规定电压条件不同的电压条件下，对一个存储块中的存储单元执行预擦除写入操作。

公开(公告)号：US6040999A

公开(公告)日：2000-03-21

申请号：US954174

申请日：1997-10-20

申请人： Yasuhiro Hotta ,  Shuichiro Kouchi

发明人： Yasuhiro Hotta ,  Shuichiro Kouchi

IPC分类号： G11C16/06 ,  G11C7/00 ,  G11C29/00 ,  G11C29/04 ,  G11C8/00

CPC分类号： G11C29/70 ,  G11C7/1012

摘要： A semiconductor memory device includes a main memory section, a redundant memory section, a memory cell selection section, a sensing amplification section, a data replacement section, and a data selection section. The redundant memory section includes a replacement cell data memory section for storing replacement cell data to replace cell data in a prescribed memory cell in the main memory section, and a control signal generation section for generating a control signal based on an input address. The memory cell selection section simultaneously selects prescribed cells as a plurality of memory cells corresponding to a prescribed page in the main memory section based on the input address. The sensing amplification section simultaneously senses cell data corresponding to a selected plurality of memory cells as page data. A supply of the replacement cell data and the control signal from the redundant memory section to the data replacement section is performed in a time period from the time when the input address is determined until a time when the page data to be output from the sensing amplification section is determined.

摘要翻译： 半导体存储器件包括主存储器部分，冗余存储器部分，存储器单元选择部分，感测放大部分，数据替换部分和数据选择部分。 冗余存储器部分包括：替换单元数据存储部分，用于存储替换单元数据以替换主存储器部分中的规定存储单元中的单元数据;以及控制信号生成单元，用于基于输入地址生成控制信号。 存储单元选择部分基于输入地址同时选择规定的单元作为与主存储器部分中的规定页面对应的多个存储单元。 感测放大部分同时感测对应于所选择的多个存储器单元的单元数据作为页数据。 在从确定输入地址到从感测放大器输出的寻呼数据的时间段的时间段内执行从冗余存储器部分到数据替换部分的替换单元数据和控制信号的供应 部分确定。

公开(公告)号：US06549465B2

公开(公告)日：2003-04-15

申请号：US10083661

申请日：2002-02-27

申请人： Yasuaki Hirano ,  Shuichiro Kouchi ,  Yoshihisa Sekiguchi

发明人： Yasuaki Hirano ,  Shuichiro Kouchi ,  Yoshihisa Sekiguchi

IPC分类号： G11C1600

CPC分类号： G11C16/30 ,  G11C16/14

摘要： A well voltage setting circuit has a P-MOS transistor for applying erase pulse, a first N-MOS transistor for applying a reference voltage Vss to a P-well in a shutdown sequence after erase pulse application, and a second N-MOS transistor for forcing the P-well to the reference voltage Vss during write and read. The first N-MOS transistor has a driving capacity set to about {fraction (1/50)} of that of the second N-MOS transistor, so that a time for forcing the P-well to the reference voltage Vss is long enough to prevent occurrence of local latch-up during erase.

公开(公告)号：US06185131B2

公开(公告)日：2001-02-06

申请号：US09578852

申请日：2000-05-26

申请人： Shuichiro Kouchi

发明人： Shuichiro Kouchi

IPC分类号： G11C1606

CPC分类号： G11C16/0416 ,  G11C5/02

摘要： A virtual-grounding memory cell array region and a virtual-grounding dummy cell array region are electrically isolated from each other while any increase in chip size is suppressed. An erase voltage Vers (−8 V) is applied to a dummy main bit line DMBL0 in a dummy cell array region 20 via an erase voltage supply transistor 2. A negative voltage (−8 V) is applied to drains of dummy cells DCELL0, DCELL0, . . . as well as sources of dummy cells DCELL1, DCELL1, . . . within a BLOCKn through dummy sub-bit lines DSBL. By electrons being injected into the floating gates of all the dummy cells DCELL in the columns of the dummy cells DCELL0 and DCELL1 within the BLOCKn, the threshold of those dummy cells DCELL becomes high. Occurrence of any charging currents and leak currents from the virtual-grounding memory cell array region to the floating capacitance of the dummy cells is prevented.

摘要翻译： 虚拟接地存储单元阵列区域和虚拟接地虚拟单元阵列区域彼此电隔离，同时可以抑制芯片尺寸的任何增加。 擦除电压Vers（-8V）经由擦除电压供给晶体管2施加到虚设电池阵列区域20中的虚设主位线DMBL0。负电压（-8V）施加到虚设电池DCELL0的漏极， DCELL0，。 。 。 以及虚拟细胞来源DCELL1，DCELL1，。 。 。 在BLOCKn内通过虚拟子位线DSBL。 通过将电子注入到BLOCKn内的虚拟单元DCELL0和DCELL1的列中的所有虚拟单元DCELL的浮置栅极中，这些虚设单元DCELL的阈值变高。 防止从虚拟接地存储单元阵列区域到虚设单元的浮动电容的任何充电电流和泄漏电流的发生。

公开(公告)号：US06831858B2

公开(公告)日：2004-12-14

申请号：US10637923

申请日：2003-08-08

申请人： Yasuaki Hirano ,  Shuichiro Kouchi

发明人： Yasuaki Hirano ,  Shuichiro Kouchi

IPC分类号： G11C1604

CPC分类号： G11C29/50004 ,  G11C11/5628 ,  G11C16/04 ,  G11C16/30 ,  G11C29/006

摘要： A non-volatile semiconductor memory device, is provided, which comprises a plurality of memory cells capable of electrically writing and erasing data and a voltage control section for controlling a control voltage to be applied to each of the plurality of row lines. The voltage control section comprises a storing section and a voltage output section. The storing section stores the value of the control voltage, which is calculated to permit a threshold voltage distribution to be within a predetermined range, in accordance with the threshold voltage distribution of the plurality of memory cells in each chip. The voltage output section outputs the control voltage having the value stored in the storing section to each of the plurality of row lines.

公开(公告)号：US06912161B2

公开(公告)日：2005-06-28

申请号：US10611643

申请日：2003-07-02

申请人： Yasuaki Hirano ,  Yasumichi Mori ,  Shuichiro Kouchi

发明人： Yasuaki Hirano ,  Yasumichi Mori ,  Shuichiro Kouchi

IPC分类号： G11C16/04 ,  G11C11/56 ,  G11C16/06 ,  G11C16/10 ,  G11C16/28

CPC分类号： G11C11/5642 ,  G11C16/10 ,  G11C16/28 ,  G11C2211/5634

摘要： In the nonvolatile semiconductor memory device of this invention, a program control circuit 1 sets the threshold value of a first reference cell RFC0 by means of a write circuit WC on the basis of a result of comparing the threshold value of the first reference cell RFC0 with the threshold value of a second reference cell SRC executed by a sense amplifier 8 for trimming. The compare of threshold values by the sense amplifier 8 for trimming can be executed within a shorter time than in the threshold value read operation of the first reference cell RFC0. Therefore, when the number of the first reference cells is increased, the threshold value adjustment time can be remarkably reduced in comparison with the prior art in which the threshold value of the first reference cell is adjusted by reading the first reference cell.

摘要翻译： 在本发明的非易失性半导体存储器件中，程序控制电路1基于比较第一参考单元RFC的阈值的结果，通过写入电路WC来设置第一参考单元RFC0的阈值 0与用于修整的读出放大器8执行的第二参考单元SRC的阈值。 可以在比第一参考单元RFC 0的阈值读取操作更短的时间内执行用于修整的读出放大器8的阈值的比较。因此，当第一参考单元的数量增加时，阈值 与通过读取第一参考单元来调整第一参考单元的阈值的现有技术相比，可以显着地减小调整时间。