公开(公告)号：US6040999A

公开(公告)日：2000-03-21

申请号：US954174

申请日：1997-10-20

申请人： Yasuhiro Hotta ,  Shuichiro Kouchi

发明人： Yasuhiro Hotta ,  Shuichiro Kouchi

IPC分类号： G11C16/06 ,  G11C7/00 ,  G11C29/00 ,  G11C29/04 ,  G11C8/00

CPC分类号： G11C29/70 ,  G11C7/1012

摘要： A semiconductor memory device includes a main memory section, a redundant memory section, a memory cell selection section, a sensing amplification section, a data replacement section, and a data selection section. The redundant memory section includes a replacement cell data memory section for storing replacement cell data to replace cell data in a prescribed memory cell in the main memory section, and a control signal generation section for generating a control signal based on an input address. The memory cell selection section simultaneously selects prescribed cells as a plurality of memory cells corresponding to a prescribed page in the main memory section based on the input address. The sensing amplification section simultaneously senses cell data corresponding to a selected plurality of memory cells as page data. A supply of the replacement cell data and the control signal from the redundant memory section to the data replacement section is performed in a time period from the time when the input address is determined until a time when the page data to be output from the sensing amplification section is determined.

摘要翻译： 半导体存储器件包括主存储器部分，冗余存储器部分，存储器单元选择部分，感测放大部分，数据替换部分和数据选择部分。 冗余存储器部分包括：替换单元数据存储部分，用于存储替换单元数据以替换主存储器部分中的规定存储单元中的单元数据;以及控制信号生成单元，用于基于输入地址生成控制信号。 存储单元选择部分基于输入地址同时选择规定的单元作为与主存储器部分中的规定页面对应的多个存储单元。 感测放大部分同时感测对应于所选择的多个存储器单元的单元数据作为页数据。 在从确定输入地址到从感测放大器输出的寻呼数据的时间段的时间段内执行从冗余存储器部分到数据替换部分的替换单元数据和控制信号的供应 部分确定。

公开(公告)号：US09266142B2

公开(公告)日：2016-02-23

申请号：US14232341

申请日：2012-09-06

申请人： Koji Hasegawa ,  Yasuhiro Hotta ,  Naotoshi Kinoshita ,  Tarou Endou ,  Shuichiro Fukuda ,  Kazuhiro Uchida ,  Yosuke Tomita ,  Hitoshi Kamada ,  Kazunori Wakabayashi

发明人： Koji Hasegawa ,  Yasuhiro Hotta ,  Naotoshi Kinoshita ,  Tarou Endou ,  Shuichiro Fukuda ,  Kazuhiro Uchida ,  Yosuke Tomita ,  Hitoshi Kamada ,  Kazunori Wakabayashi

IPC分类号： B05C9/12 ,  B05C3/08 ,  B01J2/00 ,  A23G3/20 ,  A23P1/08 ,  A23G3/26 ,  B01J2/12 ,  B01J2/14

CPC分类号： B05C9/12 ,  A23G3/2076 ,  A23G3/26 ,  A23P20/13 ,  B01J2/00 ,  B01J2/006 ,  B01J2/12 ,  B01J2/14 ,  B05C3/08

摘要： A partition portion includes a proximal portion fixed to the outer periphery of the peripheral wall portion and a sealing member mounted to the proximal portion in a manner that the sealing member is allowed to move in inner and outer circumferential directions of the peripheral wall portion. When receiving a force toward an outer circumferential direction, the sealing member is moved in the outer circumferential direction, and a distal end portion thereof is held in press-contact with a sliding contact portion of a ventilation member with a force generated along with the above-mentioned force.

摘要翻译： 分隔部包括固定在周壁部的外周的基部部分和以允许密封部件在周壁部的内周向和外周方向移动的方式安装在基部的密封部件。 当向外周方向受力时，密封构件沿外周方向移动，其前端部与通气构件的滑动接触部保持与上述同时产生的力压接 所谓的力量。

公开(公告)号：US5295092A

公开(公告)日：1994-03-15

申请号：US7197

申请日：1993-01-21

申请人： Yasuhiro Hotta

发明人： Yasuhiro Hotta

IPC分类号： G11C17/12 ,  H01L21/8246 ,  H01L27/112 ,  H01L27/115 ,  G11C13/00 ,  G11C11/40

CPC分类号： G11C17/126 ,  H01L27/112 ,  H01L27/115

摘要： A semiconductor read only memory of this invention includes a plurality of word lines disposed in parallel. The read only memory has a plurality of units. Each of the plurality of units includes: a first bit line which crosses the word lines; a plurality of first virtual ground lines disposed substantially in parallel with the first bit line, each of the plurality of first virtual ground lines having a first end and a second end; a plurality of second virtual ground lines corresponding to the plurality of first virtual ground line, each of the plurality of second virtual ground lines having a first end and a second end; second bit lines, each provided between two adjacent ones of the plurality of second virtual ground lines, each of the second bit lines having a first end and a second end; memory cell columns, each constituted by a plurality of memory cells connected in parallel between one of the second virtual ground lines and one of the second bit lines adjacent thereto; and bank select switching elements for selecting one of the memory cell columns. In the read only memory, the second ends of the plurality of first virtual ground lines are respectively connected to the second ends of the second virtual ground lines, and the first ends of the second bit lines are respectively connected to the bank select switching elements.

摘要翻译： 本发明的半导体只读存储器包括并行布置的多个字线。 只读存储器具有多个单元。 多个单元中的每一个包括：跨越字线的第一位线; 多个第一虚拟接地线，与第一位线基本平行地设置，多个第一虚拟接地线中的每一个具有第一端和第二端; 对应于多个第一虚拟接地线的多个第二虚拟接地线，所述多个第二虚拟接地线中的每一条具有第一端和第二端; 第二位线，每个设置在多个第二虚拟接地线中的两个相邻的第二虚拟接地线之间，每个第二位线具有第一端和第二端; 存储单元列，每个由多个存储单元构成，所述多个存储单元并联连接在所述第二虚拟接地线之一和与其相邻的所述第二位线中的一个之间; 以及用于选择一个存储单元列的存储体选择开关元件。 在只读存储器中，多个第一虚拟接地线的第二端分别连接到第二虚拟接地线的第二端，第二位线的第一端分别连接到组选择开关元件。

公开(公告)号：US5402387A

公开(公告)日：1995-03-28

申请号：US31177

申请日：1993-03-12

申请人： Yasuhiro Hotta

发明人： Yasuhiro Hotta

IPC分类号： G11C7/10 ,  G11C7/22 ,  G11C8/06 ,  G11C7/00

CPC分类号： G11C7/1051 ,  G11C7/22 ,  G11C8/06

摘要： A semiconductor memory including a memory cell array having a plurality of memory cells; an input buffer circuit for receiving an address signal having an amplitude at an interface level and generating at least one output signal having an amplitude at an internal logic level in accordance with said address signal, the input buffer circuit further receiving a first signal and changing the response characteristics thereof in response to the first signal; a detecting circuit for receiving the output signal and generating a detecting signal indicating whether the level of the output signal varies; and a control signal generating circuit for receiving the detecting signal and generating the first signal based on the detecting signal.

摘要翻译： 一种半导体存储器，包括具有多个存储单元的存储单元阵列; 输入缓冲器电路，用于接收具有在接口电平处的振幅的地址信号，并根据所述地址信号产生具有内部逻辑电平的振幅的至少一个输出信号，所述输入缓冲电路还接收第一信号并改变 响应于第一信号的响应特性; 检测电路，用于接收输出信号并产生指示输出信号的电平是否变化的检测信号; 以及控制信号发生电路，用于接收检测信号并根据检测信号产生第一信号。

公开(公告)号：US5280442A

公开(公告)日：1994-01-18

申请号：US781630

申请日：1991-10-22

申请人： Yasuhiro Hotta ,  Mikiro Okada

发明人： Yasuhiro Hotta ,  Mikiro Okada

IPC分类号： H01L27/112 ,  G11C17/12 ,  H01L21/8246 ,  G11C11/40

CPC分类号： G11C17/126

摘要： A read-only memory includes columns of memory cell arrays, a plurality of banks formed by dividing each column of the memory cell arrays along the columns, sub-bit lines disposed between adjacent banks situated along the rows and connected to a transistor of each memory cell, and main-bit lines disposed between every two other columns of the memory cell arrays and extending along the columns, wherein the sub-bit lines are divided into sets of three sub-bit lines connected to a pair of adjacent banks situated along the rows, and one end of each center sub-bit line being connected to a first main-bit line through a first selector transistor, the first main-bit line passing through one side of the set to which the center bit-line belongs, and the other end of the sub-bit line being connected to a second main-bit line through a second selector transistor, the second main-bit line passing through the other side of the set to which the center sub-bit line belongs, the two outer sub-bit lines being directly connected to the main-bit lines adjacent to the set of banks, respectively.

摘要翻译： 只读存储器包括存储单元阵列的列，通过沿着列划分存储单元阵列的每列形成的多个存储体，设置在沿着行的相邻存储体之间并连接到每个存储器的晶体管的子位线 单元和主位线设置在存储单元阵列的每两个其他列之间并且沿着列延伸，其中子位线被划分为连接到沿着该位置的一对相邻堤的三个子位线的集合 每个中心子位线的一端通过第一选择晶体管连接到第一主位线，第一主位线通过中心位线所属的集合的一侧，以及 子位线的另一端通过第二选择晶体管连接到第二主位线，第二主位线通过中心子位线所属的集合的另一侧，二位 外部子位线 分别直接连接到与该组存储体相邻的主位线。

公开(公告)号：US5268861A

公开(公告)日：1993-12-07

申请号：US845257

申请日：1992-03-03

申请人： Yasuhiro Hotta

发明人： Yasuhiro Hotta

IPC分类号： G11C17/18 ,  G11C17/12 ,  G11C13/00 ,  G11C11/40

CPC分类号： G11C17/126 ,  G11C17/12

摘要： A semiconductor read only memory with hierarchical bit lines in which a resistance against a discharge current is constant irrespective of the position of a memory cell from which information is to be read is disclosed. A bank selecting MOSFET is connected to one end portion of a sub-bit line. Another bank selecting MOSFET is connected to the other end portion of the adjacent sub-bit line. Bank selecting MOSFETs are connected in the same alternate manner as described above. Therefore, since the resistance on bit lines against the read-out current is constant, a larger read-out current can be used especially when diffusion bit lines are used, whereby the semiconductor read only memory of the invention can achieve a high-speed read operation.

公开(公告)号：US6081476A

公开(公告)日：2000-06-27

申请号：US119955

申请日：1998-07-21

申请人： Yasuhiro Hotta

发明人： Yasuhiro Hotta

IPC分类号： G11C7/10 ,  G11C17/00 ,  G11C17/12 ,  H01L21/8246 ,  H01L27/112 ,  G11C8/00

CPC分类号： H01L27/112 ,  G11C17/126 ,  G11C7/1045

摘要： A clock-synchronized read only memory includes: a memory cell and a mode register for setting an operation mode, the clock-synchronized read only memory outputting data stored in the memory cell in the operation mode set in the mode register and in synchronization with a clock signal. The contents of the mode register are set when the data is written to the memory cell, the contents defining the operation mode.

摘要翻译： 时钟同步的只读存储器包括：存储单元和用于设置操作模式的模式寄存器，时钟同步的只读存储器输出存储在存储器单元中的数据，并以与模式寄存器中同步的操作模式 时钟信号。 当数据被写入存储单元时，模式寄存器的内容被设置，内容定义了操作模式。

公开(公告)号：US5790466A

公开(公告)日：1998-08-04

申请号：US757928

申请日：1996-11-27

申请人： Yasuhiro Hotta

发明人： Yasuhiro Hotta

IPC分类号： G11C17/00 ,  G11C7/12 ,  G11C16/06 ,  G11C16/26 ,  G11C17/18 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C16/26

摘要： The semiconductor memory device of this invention includes a plurality of bit lines for carrying data read out from memory cells and supplying the data to a sense amplifier, the device including: a bias voltage generator for generating a first bias voltage and a second bias voltage which are different from each other; a first precharger for precharging at least one selected bit line to a first precharge voltage obtained based on the first bias voltage generated by the bias voltage generator; and a second precharger for preliminarily precharging each bit line to a second precharge voltage obtained based on the second bias voltage generated by the bias voltage generator.

摘要翻译： 本发明的半导体存储器件包括多个位线，用于承载从存储器单元读出的数据并将数据提供给读出放大器，该器件包括：偏置电压发生器，用于产生第一偏置电压和第二偏置电压， 彼此不同; 第一预充电器，用于将至少一个所选位线预充电到基于由偏置电压发生器产生的第一偏置电压获得的第一预充电电压; 以及第二预充电器，用于将每个位线预充电到基于由偏置电压发生器产生的第二偏置电压获得的第二预充电电压。

公开(公告)号：US5748561A

公开(公告)日：1998-05-05

申请号：US742338

申请日：1996-11-01

申请人： Yasuhiro Hotta

发明人： Yasuhiro Hotta

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C8/10 ,  G11C8/12 ,  G11C17/12 ,  G11C17/18 ,  G11C8/00

CPC分类号： G11C7/103 ,  G11C17/12 ,  G11C8/10 ,  G11C8/12

摘要： A semiconductor memory device of the invention includes a memory cell array having a plurality of memory cells, row selector for selecting a row of the memory cell array corresponding to a row address of an input address, and column selector for selecting a plurality of columns of a memory cell array corresponding to a column address of an input address, and also selecting a plurality of columns of a memory cell array corresponding to at least one column address other than a column address of an input address. The device also includes a sense amplifier for sensing data stored in memory cells. The sense amplifier has at least two sense amplifier groups, the sense amplifier groups sensing data read from a plurality of memory cells corresponding to an input address, and data read from a plurality of memory cells corresponding to the row address of an input address and at least one other column address. The device has a page mode for rapidly switching and outputting data from a plurality of memory cells which have been read in parallel to sense amplifier in accordance with an input address.

摘要翻译： 本发明的半导体存储器件包括具有多个存储单元的存储单元阵列，用于选择与输入地址的行地址对应的存储单元阵列的行选择器，以及用于选择多个列的列列的列选择器 对应于输入地址的列地址的存储单元阵列，并且还选择与输入地址的列地址以外的至少一个列地址对应的存储单元阵列的多个列。 该装置还包括用于感测存储在存储单元中的数据的读出放大器。 读出放大器具有至少两个读出放大器组，读出放大器组感测从对应于输入地址的多个存储单元读取的数据，以及从与输入地址的行地址相对应的多个存储单元读取的数据， 至少一个其他列地址。 该设备具有页面模式，用于根据输入地址将已经被读取并行读出放大器的多个存储器单元快速地切换和输出数据。

公开(公告)号：US5668772A

公开(公告)日：1997-09-16

申请号：US713664

申请日：1996-09-13

申请人： Yasuhiro Hotta

发明人： Yasuhiro Hotta

IPC分类号： G11C11/413 ,  G11C8/04 ,  G11C8/10 ,  G11C11/401 ,  G11C11/408 ,  G11C8/00

CPC分类号： G11C8/10

摘要： A semiconductor memory device comprising a memory cell array includes a plurality of memory cells. The device includes: a predecoder for dividing a plurality of bits of an address signal into at least two bit strings so as to decode each bit string and output predecoded results of each bit string in parallel; a series of shift registers, each shift register being provided for a respective bit string, receiving the predecoded results of the corresponding bit string as shift data, shifting the received shift data, thereby generating and outputting predecoded signal bits; and a main decoder for decoding the predecoded signal bits output from the plurality of shift registers and selecting a memory cell in the memory cell array in accordance with the results of the decoding.

摘要翻译： 包括存储单元阵列的半导体存储器件包括多个存储单元。 该装置包括：预解码器，用于将地址信号的多个比特分成至少两个比特串，以解码每个比特串并并行地输出每个比特串的预解码结果; 一系列移位寄存器，每个移位寄存器被提供给相应的比特串，接收对应比特串的预解码结果作为移位数据，移位接收到的移位数据，从而产生并输出预编码的信号比特; 以及主解码器，用于对从多个移位寄存器输出的预解码信号位进行解码，并根据解码结果选择存储单元阵列中的存储单元。