公开(公告)号：US07834461B2

公开(公告)日：2010-11-16

申请号：US11853196

申请日：2007-09-11

申请人： Shuji Asai ,  Tadachika Hidaka ,  Naoto Kurosawa ,  Hirokazu Oikawa ,  Takaki Niwa

发明人： Shuji Asai ,  Tadachika Hidaka ,  Naoto Kurosawa ,  Hirokazu Oikawa ,  Takaki Niwa

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L29/7371 ,  H01L21/76898 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor apparatus includes a semiconductor device formed to a first surface of a semiconductor substrate, a blocking film provided in a first via-hole, the first via-hole formed with a concave shape to the first surface of the semiconductor substrate, a first via line connected to an electrode of the semiconductor device in contact with the blocking film, a second via line formed inside a second via-hole, electrically connected with the first via line with the blocking film interposed therebetween and being apart of a wiring formed to a second surface, the second via-hole formed with a concave shape to the second surface opposing the first surface of the semiconductor substrate so as to reach the blocking film. The blocking film includes at least one kind of group 8 element.

摘要翻译： 半导体装置包括形成在半导体衬底的第一表面上的半导体器件，设置在第一通孔中的阻挡膜，形成有凹形的第一通孔至半导体衬底的第一表面，第一通孔 连接到与阻挡膜接触的半导体器件的电极的第二通孔线，形成在第二通孔内的第二通孔线，其中第一通孔线与插入其间的阻挡膜电连接，并且形成为 所述第二通孔形成为与所述半导体衬底的所述第一表面相对的所述第二表面具有凹形的第二通孔，以到达所述阻挡膜。 阻挡膜包括至少一种8族元素。

公开(公告)号：US6159861A

公开(公告)日：2000-12-12

申请号：US141328

申请日：1998-08-27

申请人： Shuji Asai ,  Hirokazu Oikawa

发明人： Shuji Asai ,  Hirokazu Oikawa

IPC分类号： H01L21/285 ,  H01L21/335 ,  H01L21/338 ,  H01L29/10 ,  H01L21/302

CPC分类号： H01L29/66863 ,  H01L21/28581 ,  H01L21/28587 ,  H01L29/1029 ,  H01L29/66462

摘要： In a method of manufacturing a semiconductor device which has a semiconductor substrate, a channel layer formed on the semiconductor substrate and an insulating film deposited on the channel layer, an opening corresponding to a gate electrode pattern is formed in the insulating film by the use of a photoresist film. The channel layer contains crystal components while the photo-resist film contains carbon. The insulating film is etched to exposed said channel layer after removing the photoresist film. In consequence, no reacted production is formed between the crystal components and the carbon on the exposed channel layer.

摘要翻译： 在制造具有半导体衬底的半导体器件的方法中，形成在半导体衬底上的沟道层和沉积在沟道层上的绝缘膜，在绝缘膜中形成与栅电极图案对应的开口， 光致抗蚀剂膜。 通道层含有晶体成分，而光刻胶膜含有碳。 在去除光致抗蚀剂膜之后，蚀刻绝缘膜以暴露所述沟道层。 因此，在结晶成分和暴露的沟道层上的碳之间不产生反应生成。

公开(公告)号：US6150245A

公开(公告)日：2000-11-21

申请号：US419850

申请日：1999-10-19

申请人： Shuji Asai

发明人： Shuji Asai

IPC分类号： H01L21/335 ,  H01L29/423 ,  H01L21/28 ,  H01L21/336 ,  H01L21/44

CPC分类号： H01L29/66446 ,  H01L29/42316

摘要： On a channel layer, there are disposed a gate electrode and a first contact layer of which a side surface is brought into contact with the gate electrode on the source side and of which a side surface is apart from the gate electrode on the drain side. Provided on the first contact layer is a second contact layer on which ohmic source and drain electrodes are arranged. A connection wiring is disposed on an upper end of the gate electrode. Specifically, there are provided a thin contact layer and a thick contact layer such that the thin contact layer is brought into contact with the gate electrode. Therefore, the problems of the contact resistance of the ohmic electrode and the gate parasitic capacitance are removed and both drawbacks can be improved at the same time.

摘要翻译： 在沟道层上设置有栅电极和第一接触层，其侧表面与源极侧的栅电极接触，并且侧面与漏极侧的栅极分离。 提供在第一接触层上的是第二接触层，在其上布置有欧姆源极和漏极。 连接布线设置在栅电极的上端。 具体地，提供了薄接触层和厚接触层，使得薄接触层与栅电极接触。 因此，消除了欧姆电极的接触电阻和栅极寄生电容的问题，同时可以提高两个缺点。

公开(公告)号：US6069375A

公开(公告)日：2000-05-30

申请号：US807325

申请日：1997-02-27

申请人： Shuji Asai

发明人： Shuji Asai

IPC分类号： H01L29/812 ,  H01L21/335 ,  H01L21/338 ,  H01L29/423 ,  H01L29/80

CPC分类号： H01L29/66446 ,  H01L29/42316

摘要： On a channel layer, there are disposed a gate electrode and a first contact layer of which a side surface is brought into contact with the gate electrode on the source side and of which a side surface is apart from the gate electrode on the drain side. Provided on the first contact layer is a second contact layer on which ohmic source and drain electrodes are arranged. A connection wiring is disposed on an upper end of the gate electrode. Specifically, there are provided a thin contact layer and a thick contact layer such that the thin contact layer is brought into contact with the gate electrode. Therefore, the problems of the contact resistance of the ohmic electrode and the gate parasitic capacitance are removed and both drawbacks can be improved at the same time.

摘要翻译： 在沟道层上设置有栅电极和第一接触层，其侧表面与源极侧的栅电极接触，并且侧面与漏极侧的栅极分离。 提供在第一接触层上的是第二接触层，在其上布置有欧姆源极和漏极。 连接布线设置在栅电极的上端。 具体地，提供了薄接触层和厚接触层，使得薄接触层与栅电极接触。 因此，消除了欧姆电极的接触电阻和栅极寄生电容的问题，同时可以提高两个缺点。

公开(公告)号：US4221855A

公开(公告)日：1980-09-09

申请号：US920709

申请日：1978-06-30

申请人： Daisuke Manabe ,  Shuji Asai ,  Michihisa Suga

发明人： Daisuke Manabe ,  Shuji Asai ,  Michihisa Suga

IPC分类号： G03G5/085 ,  G03G5/04

CPC分类号： G03G5/085

摘要： A sintered high sensitive electrophotographic plate free of cracks in a photoconductive layer and exfoliation of it from a substrate can be obtained by adding an inorganic material, whose melting or softening temperature is higher than a firing temperature, into a mixture composed essentially of photoconductive material and a glass binder having a softening temperature lower than the firing temperature.

摘要翻译： 通过将熔融或软化温度高于烧制温度的无机材料加入到基本上由光电导材料组成的混合物中，可以获得在光电导层中没有光电导层的裂纹和从衬底剥离的烧结的高灵敏电子照相板， 具有软化温度低于烧制温度的玻璃粘合剂。

公开(公告)号：US07851884B2

公开(公告)日：2010-12-14

申请号：US12232788

申请日：2008-09-24

申请人： Shuji Asai ,  Akira Fujihara ,  Makoto Matsunoshita ,  Naoki Sakura ,  Seiji Ichikawa

发明人： Shuji Asai ,  Akira Fujihara ,  Makoto Matsunoshita ,  Naoki Sakura ,  Seiji Ichikawa

IPC分类号： H01L23/48

CPC分类号： H01L29/7783 ,  H01L29/66462 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/12032 ,  H01L2924/13062 ,  H01L2924/00014 ,  H01L2924/00

摘要： A FET exhibiting excellent uniformity and productivity and having a low noise figure and high associated gain as high-frequency performance, a semiconductor chip having this FET and a semiconductor device having the semiconductor chip. The FET includes a GaAs substrate on which are built up an i-type GaAs layer, an i-type InGaAs two-dimensional electron gas layer and an n-type AlGaAs electron supply layer. A gate electrode is provided on and in linear Schottky contact with the n-type AlGaAs electron supply layer. A n-type InGaP etching stop layer and then an n-type GaAs contact layer at the same lateral position are built up on the n-type AlGaAs electron supply layer, these being spaced away from both sides of the gate electrode. A source electrode and a drain electrode are provided on the n-type GaAs contact layer and are spaced away from edges of the contact layer as electrodes that make band-shaped ohmic contact.

摘要翻译： 具有优异的均匀性和生产率并且具有低噪声系数和高相关增益作为高频性能的FET，具有该FET的半导体芯片和具有半导体芯片的半导体器件。 该FET包括GaAs衬底，其上构建有i型GaAs层，i型InGaAs二维电子气体层和n型AlGaAs电子供应层。 栅电极设置在与n型AlGaAs电子供应层的线性肖特基接触中。 在n型AlGaAs电子供给层上形成n型InGaP蚀刻停止层，然后在同一横向位置形成n型GaAs接触层，这些与栅电极的两侧间隔开。 源电极和漏电极设置在n型GaAs接触层上，并且与接触层的边缘间隔开，作为带状欧姆接触的电极。

公开(公告)号：US5549749A

公开(公告)日：1996-08-27

申请号：US426951

申请日：1995-04-24

申请人： Shuji Asai

发明人： Shuji Asai

IPC分类号： H01L21/20 ,  H01L21/203 ,  H01L29/205 ,  H01L31/18 ,  C30B25/18

CPC分类号： H01L31/1852 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02631 ,  H01L21/02658 ,  H01L21/02661 ,  H01L31/1804 ,  Y02E10/544 ,  Y02E10/547 ,  Y02P70/521 ,  Y10S438/933

摘要： The invention provides a semiconductor substrate comprising a substrate of a first material and a crystal growth layer formed on the substrate, the crystal growth layer being made of compound semiconductors different from the first material wherein the substrate has a surface diffusion region being heavily doped with one or more elements of the compound semiconductors. A silicon substrate receives an ion-implantation of one or more elements constituting a compound semiconductor different except for silicon at a high impurity concentration for a heat treatment at a higher temperature than a growth temperature of the compound semiconductor and subsequent cooling down to the growth temperature of the compound semiconductor followed by crystal growth of the compound semiconductor on the substrate.

公开(公告)号：US5514605A

公开(公告)日：1996-05-07

申请号：US516292

申请日：1995-08-17

申请人： Shuji Asai ,  Michihisa Kohno

发明人： Shuji Asai ,  Michihisa Kohno

IPC分类号： H01L21/8252 ,  H01L27/06 ,  H01L27/095 ,  H01L21/8232

CPC分类号： H01L21/8252 ,  H01L27/0605 ,  H01L27/095

摘要： On a semi-insulative GaAs substrate, a channel layer, an electron supply layer, a threshold voltage controlling layer, an etching stop layer, a contact layer and an insulation layer are grown. By etching the insulation layer, gate openings are formed in an E-type element region and a D-type element region. With taking the gate opening as mask, dry etching is performed for the contact layer to form openings. On the inner periphery of the openings, side wall insulation layers are formed. With masking the gate opening in the D-type element region, and with taking the side wall insulation layer as mask, the etching stop layer is etched by wet etching, and threshold voltage controlling layer is etched by isotropic dry etching. After formation of the gate electrodes, source and drain electrodes are formed. By this, damaging of crystal upon formation of recess portion by etching is eliminated to prevent degradation of characteristics. Also, a source resistance can be lowered.

摘要翻译： 在半绝缘性GaAs衬底上生长沟道层，电子供给层，阈值电压控制层，蚀刻停止层，接触层和绝缘层。 通过蚀刻绝缘层，栅极开口形成在E型元件区域和D型元件区域中。 以开口作为掩模，对接触层进行干蚀刻以形成开口。 在开口的内周上形成有侧壁绝缘层。 通过掩盖D型元件区域中的开口，并且以侧壁绝缘层为掩模，通过湿蚀刻蚀刻蚀刻停止层，并通过各向同性干蚀刻蚀刻阈值电压控制层。 在形成栅电极之后，形成源电极和漏电极。 由此，消除了通过蚀刻形成凹陷部分时的晶体损坏，以防止特性劣化。 而且，可以降低源电阻。

公开(公告)号：US20090078966A1

公开(公告)日：2009-03-26

申请号：US12232788

申请日：2008-09-24

申请人： Shuji Asai ,  Akira Fujihara ,  Makoto Matsunoshita ,  Naoki Sakura ,  Seiji Ichikawa

发明人： Shuji Asai ,  Akira Fujihara ,  Makoto Matsunoshita ,  Naoki Sakura ,  Seiji Ichikawa

IPC分类号： H01L29/778 ,  H01L23/48

CPC分类号： H01L29/7783 ,  H01L29/66462 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2924/12032 ,  H01L2924/13062 ,  H01L2924/00014 ,  H01L2924/00

摘要： A FET exhibiting excellent uniformity and productivity and having a low noise figure and high associated gain as high-frequency performance, a semiconductor chip having this FET and a semiconductor device having the semiconductor chip. The FET includes a GaAs substrate on which are built up an i-type GaAs layer, an i-type InGaAs two-dimensional electron gas layer and an n-type AlGaAs electron supply layer. A gate electrode is provided on and in linear Schottky contact with the n-type AlGaAs electron supply layer. A n-type InGaP etching stop layer and then an n-type GaAs contact layer at the same lateral position are built up on the n-type AlGaAs electron supply layer, these being spaced away from both sides of the gate electrode. A source electrode and a drain electrode are provided on the n-type GaAs contact layer and are spaced away from edges of the contact layer as electrodes that make band-shaped ohmic contact.

摘要翻译： 具有优异的均匀性和生产率并且具有低噪声系数和高相关增益作为高频性能的FET，具有该FET的半导体芯片和具有半导体芯片的半导体器件。 该FET包括GaAs衬底，其上构建有i型GaAs层，i型InGaAs二维电子气体层和n型AlGaAs电子供应层。 栅电极设置在与n型AlGaAs电子供应层的线性肖特基接触中。 在n型AlGaAs电子供给层上形成n型InGaP蚀刻停止层，然后在同一横向位置形成n型GaAs接触层，这些与栅电极的两侧间隔开。 源电极和漏电极设置在n型GaAs接触层上，并且与接触层的边缘间隔开，作为带状欧姆接触的电极。

公开(公告)号：US06420775B1

公开(公告)日：2002-07-16

申请号：US08806985

申请日：1997-02-26

申请人： Shuji Asai

发明人： Shuji Asai

IPC分类号： H01L2930

CPC分类号： H01L29/812 ,  H01L29/32 ,  H01L2224/48091 ,  H01L2224/48472 ,  H01L2224/73265 ,  H01L2924/00014

摘要： A compound semiconductor device having improved backgate voltage resistance characteristics. To improve the backgate voltage resistance of a compound semiconductor device having field effect transistors on a main surface of a semi-insulating substrate, boron ions are implanted on the rear surface to form a defect-rich layer having carrier recombination centers.

摘要翻译： 具有改进的背栅电压电阻特性的复合半导体器件。 为了提高在半绝缘基板的主面上具有场效应晶体管的复合半导体器件的背栅电压，在背面注入硼离子，形成具有载流子复合中心的缺陷丰富层。