公开(公告)号：US08385627B2

公开(公告)日：2013-02-26

申请号：US11500979

申请日：2006-08-09

申请人： Tadanobu Toba ,  Shuji Kikuchi ,  Yuichi Sakurai ,  Wen Li

发明人： Tadanobu Toba ,  Shuji Kikuchi ,  Yuichi Sakurai ,  Wen Li

IPC分类号： G06K9/00 ,  G06K7/10 ,  G01B5/28 ,  G06F11/30 ,  H04N3/14 ,  G01N21/00

CPC分类号： G06T7/0004 ,  G06T2207/30148

摘要： When an inspection apparatus of a semiconductor device repeatedly executes computation of prescribed area data, such as image processing for detecting defects, procedures for commanding, data load, computation, and data store need to be repeated the number of times of the computation. This may impose a limitation on the speeding up of the operation. In addition, when performing parallel computation by a high-capacity image processing system for handling minute images, a lot of processors are needed, resulting in an increase in cost. In order to solve the above-mentioned problems, in the invention, an inspection apparatus of a semiconductor device includes a data memory including an access section which is capable of reading and writing simultaneously, a plurality of numerical computation units, a connector for connecting the data memory and the numerical computation units, a controller for collectively controlling the contents of processing by the plurality of numerical computation units, another connector for connecting the numerical computation units and the controller, and a data transfer controller for controlling data transfer between the numerical computation units.

摘要翻译： 当半导体装置的检查装置重复执行规定区域数据的计算时，例如用于检测缺陷的图像处理，命令，数据加载，计算和数据存储的过程需要重复计算次数。 这可能对操作的加速施加限制。 此外，当通过大容量图像处理系统执行并行计算以处理微小图像时，需要许多处理器，导致成本增加。 为了解决上述问题，在本发明中，半导体装置的检查装置包括数据存储器，该数据存储器包括能够同时读写的访问部分，多个数值计算单元，连接器 数据存储器和数值计算单元，用于共同控制多个数值计算单元的处理内容的控制器，用于连接数值计算单元和控制器的另一连接器，以及用于控制数值计算之间的数据传送的数据传输控制器 单位。

公开(公告)号：US20070036421A1

公开(公告)日：2007-02-15

申请号：US11500979

申请日：2006-08-09

申请人： Tadanobu Toba ,  Shuji Kikuchi ,  Yuichi Sakurai ,  Wen Li

发明人： Tadanobu Toba ,  Shuji Kikuchi ,  Yuichi Sakurai ,  Wen Li

IPC分类号： G06K9/00

CPC分类号： G06T7/0004 ,  G06T2207/30148

摘要： When an inspection apparatus of a semiconductor device repeatedly executes computation of prescribed area data, such as image processing for detecting defects, procedures for commanding, data load, computation, and data store need to be repeated the number of times of the computation. This may impose a limitation on the speeding up of the operation. In addition, when performing parallel computation by a high-capacity image processing system for handling minute images, a lot of processors are needed, resulting in an increase in cost. In order to solve the above-mentioned problems, in the invention, an inspection apparatus of a semiconductor device includes a data memory including an access section which is capable of reading and writing simultaneously, a plurality of numerical computation units, a connector for connecting the data memory and the numerical computation units, a controller for collectively controlling the contents of processing by the plurality of numerical computation units, another connector for connecting the numerical computation units and the controller, and a data transfer controller for controlling data transfer between the numerical computation units.

摘要翻译： 当半导体装置的检查装置重复执行规定区域数据的计算时，例如用于检测缺陷的图像处理，命令，数据加载，计算和数据存储的过程需要重复计算次数。 这可能对操作的加速施加限制。 此外，当通过大容量图像处理系统执行并行计算以处理微小图像时，需要许多处理器，导致成本增加。 为了解决上述问题，在本发明中，半导体装置的检查装置包括数据存储器，该数据存储器包括能够同时读写的访问部分，多个数值计算单元，连接器 数据存储器和数值计算单元，用于共同控制多个数值计算单元的处理内容的控制器，用于连接数值计算单元和控制器的另一连接器，以及用于控制数值计算之间的数据传送的数据传输控制器 单位。

公开(公告)号：US07137055B2

公开(公告)日：2006-11-14

申请号：US11012355

申请日：2004-12-16

申请人： Katsunori Hirano ,  Shuji Kikuchi ,  Yuji Sonoda ,  Wen Li ,  Tadanobu Toba ,  Takashi Kanesaka ,  Masayuki Takahashi

发明人： Katsunori Hirano ,  Shuji Kikuchi ,  Yuji Sonoda ,  Wen Li ,  Tadanobu Toba ,  Takashi Kanesaka ,  Masayuki Takahashi

IPC分类号： G06F11/00

CPC分类号： G11C29/56004 ,  G01R31/31935 ,  G11C29/56

摘要： Semiconductor testing equipment according to the present invention comprises: an algorithmic pattern generator for generating a test pattern for testing a memory under test and applying the pattern to the memory under test; a comparator for comparing a response signal from the memory under test and an expected value from tho algorithmic pattern generator; a fail address acquisition part for storing an address of the memory under test (fail address) when a result compared by the comparator is failed; a fail address analysis part for analyzing the failed address and calculating the address to be repaired (repair address); and a cycle-pattern generator for redundancy processing for inserting the address to be repaired into a test pattern and applying the address to the memory under test, so that even when capacity of the semiconductor memory is increased, a fabrication yield thereof is raised by testing the memory after the packaging and by performing the redundancy processing of a defective.

摘要翻译： 根据本发明的半导体测试设备包括：算法模式发生器，用于产生用于测试被测存储器的测试模式并将该模式​​应用于被测存储器; 用于比较来自被测存储器的响应信号和来自tho算法模式发生器的期望值的比较器; 当由比较器比较的结果失败时，存储被测存储器的地址（故障地址）的故障地址获取部分; 用于分析故障地址并计算要修复的地址（修复地址）的故障地址分析部分; 以及用于将要修复的地址插入测试图案并将该地址应用于被测存储器的冗余处理的循环模式发生器，使得即使当半导体存储器的容量增加时，其制造成品率通过测试提高 包装后的存储器和通过执行有缺陷的冗余处理。

公开(公告)号：US20050149803A1

公开(公告)日：2005-07-07

申请号：US11012355

申请日：2004-12-16

申请人： Katsunori Hirano ,  Shuji Kikuchi ,  Yuji Sonoda ,  Wen Li ,  Tadanobu Toba ,  Takashi Kanesaka ,  Masayuki Takahashi

发明人： Katsunori Hirano ,  Shuji Kikuchi ,  Yuji Sonoda ,  Wen Li ,  Tadanobu Toba ,  Takashi Kanesaka ,  Masayuki Takahashi

IPC分类号： G01R31/28 ,  G01R31/3183 ,  G01R31/3193 ,  G11C29/44 ,  G11C29/56 ,  G11C29/00 ,  G06F11/00

CPC分类号： G11C29/56004 ,  G01R31/31935 ,  G11C29/56

摘要： Semiconductor testing equipment according to the present invention comprises: an algorithmic pattern generator for generating a test pattern for testing a memory under test and applying the pattern to the memory under test; a comparator for comparing a response signal from the memory under test and an expected value from tho algorithmic pattern generator; a fail address acquisition part for storing an address of the memory under test (fail address) when a result compared by the comparator is failed; a fail address analysis part for analyzing the failed address and calculating the address to be repaired (repair address); and a cycle-pattern generator for redundancy processing for inserting the address to be repaired into a test pattern and applying the address to the memory under test, so that even when capacity of the semiconductor memory is increased, a fabrication yield thereof is raised by testing the memory after the packaging and by performing the redundancy processing of a defective.

摘要翻译： 根据本发明的半导体测试设备包括：算法模式发生器，用于产生用于测试被测存储器的测试模式并将该模式​​应用于被测存储器; 用于比较来自被测存储器的响应信号和来自tho算法模式发生器的期望值的比较器; 当由比较器比较的结果失败时，存储被测存储器的地址（故障地址）的故障地址获取部分; 用于分析故障地址并计算要修复的地址（修复地址）的故障地址分析部分; 以及用于将要修复的地址插入测试图案并将该地址应用于被测存储器的冗余处理的循环模式发生器，使得即使当半导体存储器的容量增加时，其制造成品率通过测试提高 包装后的存储器和通过执行有缺陷的冗余处理。

公开(公告)号：US09506603B2

公开(公告)日：2016-11-29

申请号：US13615988

申请日：2012-09-14

申请人： Wen Li ,  John J. Vajo ,  Alan J. Jacobsen ,  Mei Cai ,  Martin P. Sulic

发明人： Wen Li ,  John J. Vajo ,  Alan J. Jacobsen ,  Mei Cai ,  Martin P. Sulic

IPC分类号： F17C11/00

CPC分类号： F17C11/005 ,  Y02E60/321 ,  Y10T29/49826

摘要： One illustrative embodiment includes materials and devices including an integrated hydrogen storage structure including a plurality of continuously connected thermally conductive elongated members, the elongated members including continuously connected openings between the elongated members; and, a metal hydride material contacting the elongated members and disposed within the connected openings and surrounding the elongated members.

摘要翻译： 一个说明性实施例包括包括包括多个连续连接的导热细长构件的集成氢存储结构的材料和装置，细长构件包括在细长构件之间的连续连接的开口; 以及金属氢化物材料，其与细长构件接触并且设置在连接的开口内并围绕细长构件。

公开(公告)号：US09126834B2

公开(公告)日：2015-09-08

申请号：US12615524

申请日：2009-11-10

申请人： Wen Li ,  Adam F. Gross ,  Alan J. Jacobsen ,  John J. Vajo

发明人： Wen Li ,  Adam F. Gross ,  Alan J. Jacobsen ,  John J. Vajo

IPC分类号： C01B31/02 ,  B82Y30/00 ,  C01B3/00 ,  B01J20/20 ,  B01J20/02

CPC分类号： C01B31/02 ,  B01J20/0203 ,  B01J20/20 ,  B82Y30/00 ,  C01B3/0021 ,  C01B3/0026 ,  C01B3/0031 ,  C01B3/0036 ,  C01B3/0042 ,  C01B3/0047 ,  C01B3/0057 ,  C01B3/0068 ,  C01B3/0084 ,  C01B32/05 ,  Y02E60/325 ,  Y02E60/327

摘要： A hydrogen storage material has been developed that comprises a metal hydride material embedded into a carbon microstructure that generally exhibits a greater bulk thermal conductivity than the surrounding bulk metal hydride material.

摘要翻译： 已经开发了一种储氢材料，其包含嵌入到碳微结构中的金属氢化物材料，其通常表现出比周围的体金属氢化物材料更大的体积导热系数。

公开(公告)号：US08764966B2

公开(公告)日：2014-07-01

申请号：US13293432

申请日：2011-11-10

申请人： John J. Vajo ,  Wen Li ,  Ping Liu ,  Frederick E. Pinkerton

发明人： John J. Vajo ,  Wen Li ,  Ping Liu ,  Frederick E. Pinkerton

IPC分类号： C25B1/02 ,  C25B11/04

CPC分类号： C25B1/02 ,  C25D11/04 ,  H01M8/04216 ,  H01M8/0656

摘要： Both the reaction of hydride-forming compositions with hydrogen to form hydrides, and the decomposition of such hydrides to release hydrogen may be promoted electrochemically. These reactions may be conducted reversibly, and if performed in a suitable cell, the cell will serve as a hydrogen storage and release device.

摘要翻译： 氢化物形成组合物与氢形成氢化物的反应以及这种氢化物分解以释放氢，可以电化学地促进。 这些反应可以可逆地进行，并且如果在合适的电池中进行，则电池将用作储氢和释放装置。

公开(公告)号：US20140125398A1

公开(公告)日：2014-05-08

申请号：US14122623

申请日：2012-05-24

申请人： Wen Li ,  Norio Chujo ,  Masami Makuuchi ,  Takehito Kamimura

发明人： Wen Li ,  Norio Chujo ,  Masami Makuuchi ,  Takehito Kamimura

IPC分类号： H03K19/0175

CPC分类号： H03K19/0175 ,  H01L2224/48137 ,  H01L2924/181 ,  H03F1/52 ,  H03F3/195 ,  H03F3/211 ,  H03F3/3022 ,  H03F2200/189 ,  H03K19/017509 ,  H01L2924/00012

摘要： Provided is a configuration of a driver integrated circuit that can output a voltage exceeding the withstand voltage of a process, and that satisfies required apparatus performance (high speed and high voltage). A differential input circuit, a level shift circuit, and an output circuit are manufactured by the same process and divided and disposed on three or more chips with different substrate potentials (sub-potentials). By setting different applied voltages to the substrates of the chips, an output voltage greater than the process withstand voltage can be provided (see FIG. 2).

摘要翻译： 提供可以输出超过工艺耐压的电压并满足所需设备性能（高速和高电压）的驱动器集成电路的结构。 差分输入电路，电平移位电路和输出电路通过相同的工艺制造并且被分配和布置在具有不同衬底电位（子电位）的三个或更多个芯片上。 通过对芯片的基板设置不同的施加电压，可以提供大于工艺耐受电压的输出电压（参见图2）。

公开(公告)号：US08495341B2

公开(公告)日：2013-07-23

申请号：US12707163

申请日：2010-02-17

申请人： Fadi Busaba ,  Brian Curran ,  Bruce Giamei ,  Christian Jacobi ,  Wen Li

发明人： Fadi Busaba ,  Brian Curran ,  Bruce Giamei ,  Christian Jacobi ,  Wen Li

IPC分类号： G06F9/30

CPC分类号： G06F9/30032 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/3017

摘要： A method, information processing system, and computer program product manage variable operand length instructions. At least one variable operand length instruction is received. The at least one variable operand length instruction is analyzed. A length of at least one operand in the variable operand length instruction is identified based on the analyzing. The at least one variable operand length instruction is organized into a set of unit of operations. The set of unit of operations are executed. The executing increases one or more performance metrics of the at least one variable operand length instruction.

摘要翻译： 一种方法，信息处理系统和计算机程序产品管理可变操作数长度指令。 接收至少一个可变操作数长度指令。 分析至少一个可变操作数长度指令。 基于分析来识别可变操作数长度指令中的至少一个操作数的长度。 所述至少一个可变操作数长度指令被组织成一组操作单元。 执行操作单元的集合。 所述执行增加所述至少一个可变操作数长度指令的一个或多个性能度量。

公开(公告)号：US20130168796A1

公开(公告)日：2013-07-04

申请号：US13343146

申请日：2012-01-04

申请人： Abdelaziz Ikhlef ,  Wen Li

发明人： Abdelaziz Ikhlef ,  Wen Li

IPC分类号： H01L27/146 ,  H01L31/18

CPC分类号： H01L27/14658 ,  A61B6/032 ,  A61B6/037 ,  A61B6/4233 ,  H01L23/481 ,  H01L27/1446 ,  H01L27/14636 ,  H01L27/14663 ,  H01L31/105 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2224/05552

摘要： Photodiode arrays and methods of fabrication are provided. One photodiode array includes a silicon wafer having a first surface and an opposite second surface. The photodiode array also includes a plurality of refilled conductive vias through the silicon wafer, wherein the refilled conductive vias have a doping type different than the doping type of the substrate, and an interface between the refilled conductive vias and the substrate form diode junctions. The photodiode array further includes a patterned doped layer on the first surface overlapping the refilled conductive vias, wherein the patterned doped layer defines an array of photodiodes.

摘要翻译： 提供了光电二极管阵列和制造方法。 一个光电二极管阵列包括具有第一表面和相对的第二表面的硅晶片。 光电二极管阵列还包括通过硅晶片的多个重新填充的导电通孔，其中重新填充的导电通孔具有不同于衬底的掺杂类型的掺杂类型，并且再填充的导电通孔和衬底之间的界面形成二极管结。 光电二极管阵列还包括在重新填充的导电通孔上的第一表面上的图案化掺杂层，其中图案化掺杂层限定光电二极管阵列。