公开(公告)号：US08084306B2

公开(公告)日：2011-12-27

申请号：US12409968

申请日：2009-03-24

申请人： Jae-Hun Jeong ,  Hoon Lim ,  Soon-Moon Jung ,  Hoo-Sung Cho

发明人： Jae-Hun Jeong ,  Hoon Lim ,  Soon-Moon Jung ,  Hoo-Sung Cho

IPC分类号： H01L21/00 ,  H01L21/84

CPC分类号： H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/783 ,  H01L29/78606 ,  H01L29/78654

摘要： A semiconductor device includes a body region having a source region, a drain region, a channel region interposed between the source region and the drain region, and a body region extension extending from an end of the channel region. A gate pattern is formed on the channel region and the body region, and a body contact connects the gate pattern to the body region. A sidewall of the body region extension is self-aligned to a sidewall of the gate pattern. Methods of forming semiconductor devices having a self-aligned body and a body contact are also disclosed.

摘要翻译： 半导体器件包括具有源极区域，漏极区域，插入在源极区域和漏极区域之间的沟道区域的主体区域以及从沟道区域的端部延伸的主体区域延伸部。 在沟道区域和体区域上形成栅极图案，并且体接触将栅极图案连接到身体区域。 身体区域延伸部的侧壁与栅极图案的侧壁自对准。 还公开了具有自对准体和身体接触的半导体器件的形成方法。

公开(公告)号：US20110300683A1

公开(公告)日：2011-12-08

申请号：US13137420

申请日：2011-08-15

申请人： Jun-Beom Park ,  Soon-Moon Jung ,  Ki-Nam Kim

发明人： Jun-Beom Park ,  Soon-Moon Jung ,  Ki-Nam Kim

IPC分类号： H01L45/00

CPC分类号： H01L27/24 ,  Y10S977/774

摘要： A semiconductor device and a method of forming the same are provided. The method includes preparing a semiconductor substrate. Insulating layers may be sequentially formed on the semiconductor substrate. Active elements may be formed between the insulating layers. A common node may be formed in the insulating layers to be electrically connected to the active elements. The common node and the active elements may be 2-dimensionally and repeatedly arranged on the semiconductor substrate.

公开(公告)号：US08034668B2

公开(公告)日：2011-10-11

申请号：US12588240

申请日：2009-10-08

申请人： Young-Chul Jang ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Yang-Soo Son ,  Min-Sung Song

发明人： Young-Chul Jang ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Yang-Soo Son ,  Min-Sung Song

IPC分类号： H01L21/76

CPC分类号： H01L27/0688 ,  H01L27/105 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

摘要： A semiconductor device includes a semiconductor substrate including a first region having a cell region and a second region having a peripheral circuit region, first transistors on the semiconductor substrate, a first protective layer covering the first transistors, a first insulation layer on the first protective layer, a semiconductor pattern on the first insulation layer in the first region, second transistors on the semiconductor pattern, a second protective layer covering the second transistors, the second protective layer having a thickness greater than that of the first protective layer, and a second insulation layer on the second protective layer and the first insulation layer of the second region.

摘要翻译： 半导体器件包括：半导体衬底，包括具有单元区域的第一区域和具有外围电路区域的第二区域;半导体衬底上的第一晶体管;覆盖第一晶体管的第一保护层;第一保护层上的第一绝缘层; ，第一区域中的第一绝缘层上的半导体图案，半导体图案上的第二晶体管，覆盖第二晶体管的第二保护层，第二保护层的厚度大于第一保护层的厚度，第二绝缘层 在第二保护层和第二区域的第一绝缘层上。

公开(公告)号：US07927932B2

公开(公告)日：2011-04-19

申请号：US12923471

申请日：2010-09-23

申请人： Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim ,  Cha-Dong Yeo ,  Byoung-Keun Son ,  Jae-Joo Shim ,  Chang-Min Hong

发明人： Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim ,  Cha-Dong Yeo ,  Byoung-Keun Son ,  Jae-Joo Shim ,  Chang-Min Hong

IPC分类号： H01L21/84

CPC分类号： H01L21/8221 ,  H01L27/0688 ,  H01L27/1108 ,  H01L27/1207

摘要： A semiconductor device according to example embodiments may have a plurality of stacked transistors. The semiconductor device may have a lower insulating layer formed on a semiconductor substrate and an upper channel body pattern formed on the lower insulating layer. A source region and a drain region may be formed within the upper channel body pattern, and a non-metal transfer gate electrode may be disposed on the upper channel body pattern between the source and drain regions. The non-metal transfer gate electrode, the upper channel body pattern, and the lower insulating layer may be covered by an intermediate insulating layer. A metal word line may be disposed within the intermediate insulating layer to contact at least an upper surface of the non-metal transfer gate electrode. An insulating spacer may be disposed on a sidewall of the metal word line. A metal node plug may be disposed within the intermediate insulating layer and the lower insulating layer to contact the source region of the upper channel body pattern. Example embodiments also relate to a method of fabricating the above semiconductor device.

摘要翻译： 根据示例性实施例的半导体器件可以具有多个堆叠的晶体管。 半导体器件可以具有形成在半导体衬底上的下绝缘层和形成在下绝缘层上的上沟道体图案。 源极区域和漏极区域可以形成在上部通道主体图案内，并且非金属转移栅极电极可以设置在源极和漏极区域之间的上部通道主体图案上。 非金属转移栅电极，上通道体图案和下绝缘层可以被中间绝缘层覆盖。 金属字线可以设置在中间绝缘层内以接触非金属转移栅电极的至少上表面。 绝缘间隔物可以设置在金属字线的侧壁上。 金属节点插头可以设置在中间绝缘层和下绝缘层内以接触上通道主体图案的源区域。 示例性实施例还涉及制造上述半导体器件的方法。

公开(公告)号：US07910433B2

公开(公告)日：2011-03-22

申请号：US12478538

申请日：2009-06-04

申请人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

发明人： Young-Chul Jang ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/84

CPC分类号： H01L27/105 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

摘要： A nonvolatile memory device includes a semiconductor substrate having a first well region of a first conductivity type, and at least one semiconductor layer formed on the semiconductor substrate. A first cell array is formed on the semiconductor substrate, and a second cell array formed on the semiconductor layer. The semiconductor layer includes a second well region of the first conductivity type having a doping concentration greater than a doping concentration of the first well region of the first conductivity type. As the doping concentration of the second well region is increased, a resistance difference may be reduced between the first and second well regions.

摘要翻译： 非易失性存储器件包括具有第一导电类型的第一阱区和形成在半导体衬底上的至少一个半导体层的半导体衬底。 第一单元阵列形成在半导体衬底上，第二单元阵列形成在半导体层上。 半导体层包括第一导电类型的第二阱区，其具有大于第一导电类型的第一阱区的掺杂浓度的掺杂浓度。 随着第二阱区域的掺杂浓度增加，可以在第一和第二阱区域之间减小电阻差。

公开(公告)号：US20110014754A1

公开(公告)日：2011-01-20

申请号：US12923471

申请日：2010-09-23

申请人： Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim ,  Cha-Dong Yeo ,  Byoung-Keun Son ,  Jae-Joo Shim ,  Chang-Min Hong

发明人： Han-Byung Park ,  Soon-Moon Jung ,  Hoon Lim ,  Cha-Dong Yeo ,  Byoung-Keun Son ,  Jae-Joo Shim ,  Chang-Min Hong

IPC分类号： H01L21/8234

CPC分类号： H01L21/8221 ,  H01L27/0688 ,  H01L27/1108 ,  H01L27/1207

摘要： A semiconductor device according to example embodiments may have a plurality of stacked transistors. The semiconductor device may have a lower insulating layer formed on a semiconductor substrate and an upper channel body pattern formed on the lower insulating layer. A source region and a drain region may be formed within the upper channel body pattern, and a non-metal transfer gate electrode may be disposed on the upper channel body pattern between the source and drain regions. The non-metal transfer gate electrode, the upper channel body pattern, and the lower insulating layer may be covered by an intermediate insulating layer. A metal word line may be disposed within the intermediate insulating layer to contact at least an upper surface of the non-metal transfer gate electrode. An insulating spacer may be disposed on a sidewall of the metal word line. A metal node plug may be disposed within the intermediate insulating layer and the lower insulating layer to contact the source region of the upper channel body pattern. Example embodiments also relate to a method of fabricating the above semiconductor device.

公开(公告)号：US07709323B2

公开(公告)日：2010-05-04

申请号：US12474896

申请日：2009-05-29

申请人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jong-Hyuk Kim ,  Jae-Hun Jeong ,  Jae-Hoon Jang

发明人： Hoo-Sung Cho ,  Soon-Moon Jung ,  Won-Seok Cho ,  Jong-Hyuk Kim ,  Jae-Hun Jeong ,  Jae-Hoon Jang

IPC分类号： H01L21/336

CPC分类号： H01L27/11524 ,  H01L27/0688 ,  H01L27/11551

摘要： Methods of forming a NAND-type nonvolatile memory device include: forming first common drains and first common sources alternatively in an active region which is defined in a semiconductor substrate and extends one direction, forming a first insulating layer covering an entire surface of the semiconductor substrate, patterning the first insulating layer to form seed contact holes which are arranged at regular distance and expose the active region, forming a seed contact structure filling each of the seed contact holes and a semiconductor layer disposed on the first insulating layer and contacting the seed contact structures, patterning the semiconductor layer to form a semiconductor pattern which extends in the one direction and is disposed over the active region, forming second common drains and second common sources disposed alternatively in the semiconductor pattern in the one direction, forming a second insulating layer covering an entire surface of the semiconductor substrate, forming a source line pattern continuously penetrating the second insulating layer, the semiconductor pattern and the first insulating layer, the source line pattern being connected with the first and second common sources, wherein a grain boundary of the semiconductor layer is positioned at a center between the one pair of seed contact structures adjacent to each other, and is positioned over the first common drain or the first common source.

摘要翻译： 形成NAND型非易失性存储器件的方法包括：在半导体衬底中限定的有源区域中交替形成第一公共漏极和第一公共源，并延伸一个方向，形成覆盖半导体衬底的整个表面的第一绝缘层 图案化第一绝缘层以形成以规则距离布置的暴露有源区域的种子接触孔，形成填充每个种子接触孔的种子接触结构以及设置在第一绝缘层上并接触种子接触的半导体层 结构，图案化所述半导体层以形成在所述一个方向上延伸并设置在所述有源区上方的半导体图案，形成沿所述一个方向交替设置在所述半导体图案中的第二公共漏极和第二公共源，形成第二绝缘层覆盖层 半导体衬底的整个表面 使源极线图案连续地穿过第二绝缘层，半导体图案和第一绝缘层，源极线图案与第一和第二共用源连接，其中半导体层的晶界位于第二绝缘层之间的中心 一对种子接触结构彼此相邻，并且位于第一公共漏极或第一公共源的上方。

公开(公告)号：US07683404B2

公开(公告)日：2010-03-23

申请号：US11709234

申请日：2007-02-22

申请人： Young-Chul Jang ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Hoo-Sung Cho ,  Jong-Hyuk Kim

发明人： Young-Chul Jang ,  Won-Seok Cho ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Hoo-Sung Cho ,  Jong-Hyuk Kim

IPC分类号： H01L25/065

CPC分类号： H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

摘要： A stacked memory includes at least two semiconductor layers each including a memory cell array. A transistor is formed in a peripheral circuit region of an uppermost semiconductor layer of the at least two semiconductor layers. The transistor is used to operate the memory cell array.

摘要翻译： 堆叠存储器包括至少两个半导体层，每个半导体层包括存储单元阵列。 晶体管形成在至少两个半导体层的最上半导体层的外围电路区域中。 晶体管用于操作存储单元阵列。

公开(公告)号：US07671389B2

公开(公告)日：2010-03-02

申请号：US11385473

申请日：2006-03-21

申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Young-Seop Rah ,  Han-Byung Park

发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Young-Seop Rah ,  Han-Byung Park

IPC分类号： H01L31/112

CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1116

摘要： An SRAM device includes a substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region, a plurality of stacked cell gate patterns in the cell array region, and a plurality of peripheral gate patterns disposed on the peripheral active regions in the peripheral circuit region. Metal silicide layers are disposed on at least one portion of the peripheral gate patterns and on the semiconductor substrate near the peripheral gate patterns, and buried layer patterns are disposed on the peripheral gate patterns and on at least a portion of the metal silicide layers and the portions of the semiconductor substrate near the peripheral gate patterns. An etch stop layer and a protective interlayer-insulating layer are disposed around the peripheral gate patterns and on the cell array region. Methods of forming an SRAM device are also disclosed.

摘要翻译： SRAM器件包括：在单元阵列区域中具有至少一个单元有源区和外围电路区中的多个外围有源区，单元阵列区中的多个堆叠单元栅极图案和多个外围栅极的基板 设置在外围电路区域的外围有源区上的图案。 金属硅化物层设置在外围栅极图案的至少一部分上以及半导体衬底附近的外围栅极图案上，并且掩埋层图案设置在外围栅极图案和金属硅化物层的至少一部分上，并且 半导体衬底在周边栅极图案附近的部分。 蚀刻停止层和保护性层间绝缘层设置在周围栅极图案和电池阵列区域周围。 还公开了形成SRAM器件的方法。

公开(公告)号：US20100012997A1

公开(公告)日：2010-01-21

申请号：US12499980

申请日：2009-07-09

申请人： Young-Chul JANG ,  Han-Soo KIM ,  Jae-Hun JEONG ,  Soon-Moon JUNG

发明人： Young-Chul JANG ,  Han-Soo KIM ,  Jae-Hun JEONG ,  Soon-Moon JUNG

IPC分类号： H01L29/788

CPC分类号： H01L27/11578 ,  H01L27/11524 ,  H01L27/11551 ,  H02J2007/0049

摘要： Disclosed are a flash memory device and method of operation. The flash memory device includes a bottom memory cell array and a top memory cell array disposed over the bottom memory cell array. The bottom memory cell array includes a bottom semiconductor layer, a bottom well, and a plurality of bottom memory cell units. The top memory cell array includes a top semiconductor layer, a top well, and a plurality of top memory cell units. A well bias line is disposed over the top memory cell array and includes a bottom well bias line and a top well bias line, The bottom well bias line is electrically connected to the bottom well, and the top well bias line is electrically connected to the top well.

摘要翻译： 公开了闪存装置和操作方法。 闪速存储器件包括底部存储单元阵列和设置在底部存储单元阵列上的顶部存储器单元阵列。 底部存储单元阵列包括底部半导体层，底部阱以及多个底部存储单元单元。 顶部存储单元阵列包括顶部半导体层，顶部阱以及多个顶部存储单元。 井顶偏置线设置在顶部存储单元阵列上，并且包括底部阱偏置线和顶部阱偏置线。底部阱偏置线电连接到底部阱，并且顶部阱偏置线电连接到 顶好