Method for forming capacitor
    2.
    发明授权
    Method for forming capacitor 失效
    电容器形成方法

    公开(公告)号:US06472269B2

    公开(公告)日:2002-10-29

    申请号:US10096962

    申请日:2002-03-14

    IPC分类号: H01L218242

    CPC分类号: H01L28/84

    摘要: The present invention relates to a method for fabricating a capacitor of a semiconductor device to prevent an occurrence of an operational failure of a capacitor caused by the cleaning steps that follow the process of doping PH3 into an HSG. This improves the quality of the fabricated capacitor and simplifies the operational processes of manufacture. The method includes the steps of forming an insulating interlayer over a semiconductor substrate, forming a buried contact hole in the insulating interlayer to expose a predetermined portion of the semiconductor substrate, forming a lower electrode over the insulating interlayer and in the buried contact hole, performing a first cleaning process, growing an HSG on an exposed portion of the lower electrode, performing a second cleaning process, doping PH3 into the HSG, and forming a dielectric layer over the HSG and the lower electrode. These last two steps, and in some cases the last three steps, are performed in a single process chamber without breaking up of a vacuum state of a process chamber.

    摘要翻译: 本发明涉及一种用于制造半导体器件的电容器的方法,以防止随着将PH3掺入HSG中的清洗步骤引起的电容器操作故障的发生。 这提高了制造的电容器的质量,并简化了制造的操作过程。 该方法包括以下步骤:在半导体衬底上形成绝缘中间层,在绝缘中间层中形成掩埋接触孔,露出半导体衬底的预定部分,在绝缘中间层和掩埋接触孔中形成下电极,执行 第一清洗过程,在下电极的暴露部分上生长HSG,执行第二清洗处理,将PH3掺入HSG中,以及在HSG和下电极上形成电介质层。 这些最后两个步骤,在某些情况下,最后三个步骤,在单个处理室中进行,而不会破坏处理室的真空状态。

    Method for forming a capacitor
    3.
    发明授权
    Method for forming a capacitor 失效
    电容器形成方法

    公开(公告)号:US06391715B1

    公开(公告)日:2002-05-21

    申请号:US09697515

    申请日:2000-10-27

    IPC分类号: H01L218242

    CPC分类号: H01L28/84

    摘要: The present invention relates to a method for fabricating a capacitor of a semiconductor device to prevent an occurrence of an operational failure of a capacitor caused by the cleaning steps that follow the process of doping PH3 into an HSG. This improves the quality of the fabricated capacitor and simplifies the operational processes of manufacture. The method includes the steps of forming an insulating interlayer over a semiconductor substrate, forming a buried contact hole in the insulating interlayer to expose a predetermined portion of the semiconductor substrate, forming a lower electrode over the insulating interlayer and in the buried contact hole, performing a first cleaning process, growing an HSG on an exposed portion of the lower electrode, performing a second cleaning process, doping PH3 into the HSG, and forming a dielectric layer over the HSG and the lower electrode. These last two steps, and in some cases the last three steps, are performed in a single process chamber without breaking up of a vacuum state of a process chamber.

    摘要翻译: 本发明涉及一种用于制造半导体器件的电容器的方法,以防止随着将PH3掺入HSG中的清洗步骤引起的电容器操作故障的发生。 这提高了制造的电容器的质量,并简化了制造的操作过程。 该方法包括以下步骤:在半导体衬底上形成绝缘中间层,在绝缘中间层中形成掩埋接触孔,露出半导体衬底的预定部分,在绝缘中间层和掩埋接触孔中形成下电极,执行 第一清洗过程,在下电极的暴露部分上生长HSG,执行第二清洗处理,将PH3掺入HSG中,以及在HSG和下电极上形成电介质层。 这些最后两个步骤,在某些情况下,最后三个步骤,在单个处理室中进行,而不会破坏处理室的真空状态。

    Method of doping and HSG surface of a capacitor electrode with PH3 under a low temperature/high pressure processing condition
    4.
    发明授权
    Method of doping and HSG surface of a capacitor electrode with PH3 under a low temperature/high pressure processing condition 失效
    在低温/高压处理条件下,PH3电容器电极掺杂和HSG表面的方法

    公开(公告)号:US06265264B1

    公开(公告)日:2001-07-24

    申请号:US09548013

    申请日:2000-04-12

    IPC分类号: H01L218242

    摘要: A method of fabricating a capacitor of a semiconductor device maximizes the imurity density of HSG formed at a surface of an electrode of the capacitor and thereby improves capacitance and breakdown voltage characteristics of a DRAM device incorporating the same. The method includes forming an inter-level insulating layer having a buried contact hole which exposes the underlying semiconductor substrate, forming an amorphous polysilicon layer doped with a low density of a p-type impurity on the resultant structure, selectively etching the polysilicon layer with a mask having a pattern configured to form a bottom electrode over a predetermined portion of the inter-level insulating layer which includes the contact hole, causing HSG to grow on the exposed surface of the bottom electrode, and doping PH3 into the HSG under a “low temperature/ high pressure” process condition.

    摘要翻译: 制造半导体器件的电容器的方法使形成在电容器的电极表面的HSG的非均匀密度最大化,从而提高了包含该电容器的DRAM器件的电容和击穿电压特性。 该方法包括形成具有掩埋接触孔的层间绝缘层,该掩埋接触孔暴露下面的半导体衬底,在所得结构上形成掺杂有低密度p型杂质的非晶多晶硅层,选择性地用 掩模,其具有被配置为在包括接触孔的层间绝缘层的预定部分上形成底部电极,使得HSG在底部电极的暴露表面上生长,并且在“低”下将PH3掺入到HSG中 温度/高压“工艺条件。