公开(公告)号：US20140145273A1

公开(公告)日：2014-05-29

申请号：US14088650

申请日：2013-11-25

申请人： Sung-Dae Suk ,  Changwoo Oh ,  Sungil Park

发明人： Sung-Dae Suk ,  Changwoo Oh ,  Sungil Park

IPC分类号： H01L27/088

CPC分类号： H01L27/0924 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/0922

摘要： Semiconductor devices including a first transistor and a second transistor are integrated on a substrate. Each of the first and second transistors include a nano-sized active region including source and drain regions provided in respective end portions of the nano-sized active region and a channel forming region provided between the source and drain regions. The source and drain regions of the first transistor have the same conductivity type as those of the second transistor, and the second transistor has a threshold voltage lower than that of the first transistor. The channel forming region of the second transistor may include a homogeneously doped region, whose conductivity type is the same as the source and drain regions of the second transistor and is different from the channel forming region of the first transistor.

摘要翻译： 包括第一晶体管和第二晶体管的半导体器件集成在基板上。 第一和第二晶体管中的每一个包括纳米尺寸的有源区，其包括设置在纳米尺寸有源区的相应端部中的源极和漏极区以及设置在源极和漏极区之间的沟道形成区。 第一晶体管的源极和漏极区域具有与第二晶体管相同的导电类型，并且第二晶体管具有低于第一晶体管的阈值电压的阈值电压。 第二晶体管的沟道形成区域可以包括均匀掺杂区域，其导电类型与第二晶体管的源极和漏极区域相同，并且与第一晶体管的沟道形成区域不同。

公开(公告)号：US09171845B2

公开(公告)日：2015-10-27

申请号：US14698338

申请日：2015-04-28

申请人： Sung-Dae Suk ,  Changwoo Oh ,  Sungil Park

发明人： Sung-Dae Suk ,  Changwoo Oh ,  Sungil Park

IPC分类号： H01L31/119 ,  H01L27/092 ,  H01L27/088 ,  H01L21/8234

CPC分类号： H01L27/0924 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/0922

摘要： Semiconductor devices including a first transistor and a second transistor are integrated on a substrate. Each of the first and second transistors include a nano-sized active region including source and drain regions provided in respective end portions of the nano-sized active region and a channel forming region provided between the source and drain regions. The source and drain regions of the first transistor have the same conductivity type as those of the second transistor, and the second transistor has a threshold voltage lower than that of the first transistor. The channel forming region of the second transistor may include a homogeneously doped region, whose conductivity type is the same as the source and drain regions of the second transistor and is different from the channel forming region of the first transistor.

摘要翻译： 包括第一晶体管和第二晶体管的半导体器件集成在基板上。 第一和第二晶体管中的每一个包括纳米尺寸的有源区，其包括设置在纳米尺寸有源区的相应端部中的源极和漏极区以及设置在源极和漏极区之间的沟道形成区。 第一晶体管的源极和漏极区域具有与第二晶体管相同的导电类型，并且第二晶体管具有低于第一晶体管的阈值电压的阈值电压。 第二晶体管的沟道形成区域可以包括均匀掺杂区域，其导电类型与第二晶体管的源极和漏极区域相同，并且与第一晶体管的沟道形成区域不同。

公开(公告)号：US20150243664A1

公开(公告)日：2015-08-27

申请号：US14698338

申请日：2015-04-28

申请人： Sung-Dae SUK ,  Changwoo Oh ,  Sungil Park

发明人： Sung-Dae SUK ,  Changwoo Oh ,  Sungil Park

IPC分类号： H01L27/092

CPC分类号： H01L27/0924 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/0922

摘要： Semiconductor devices including a first transistor and a second transistor are integrated on a substrate. Each of the first and second transistors include a nano-sized active region including source and drain regions provided in respective end portions of the nano-sized active region and a channel forming region provided between the source and drain regions. The source and drain regions of the first transistor have the same conductivity type as those of the second transistor, and the second transistor has a threshold voltage lower than that of the first transistor. The channel forming region of the second transistor may include a homogeneously doped region, whose conductivity type is the same as the source and drain regions of the second transistor and is different from the channel forming region of the first transistor.

摘要翻译： 包括第一晶体管和第二晶体管的半导体器件集成在基板上。 第一和第二晶体管中的每一个包括纳米尺寸的有源区，其包括设置在纳米尺寸有源区的相应端部中的源极和漏极区以及设置在源极和漏极区之间的沟道形成区。 第一晶体管的源极和漏极区域具有与第二晶体管相同的导电类型，并且第二晶体管具有低于第一晶体管的阈值电压的阈值电压。 第二晶体管的沟道形成区域可以包括均匀掺杂区域，其导电类型与第二晶体管的源极和漏极区域相同，并且与第一晶体管的沟道形成区域不同。

公开(公告)号：US09048120B2

公开(公告)日：2015-06-02

申请号：US14088650

申请日：2013-11-25

申请人： Sung-Dae Suk ,  Changwoo Oh ,  Sungil Park

发明人： Sung-Dae Suk ,  Changwoo Oh ,  Sungil Park

IPC分类号： H01L31/119 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L27/0924 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0883 ,  H01L27/0886 ,  H01L27/0922

摘要： Semiconductor devices including a first transistor and a second transistor are integrated on a substrate. Each of the first and second transistors include a nano-sized active region including source and drain regions provided in respective end portions of the nano-sized active region and a channel forming region provided between the source and drain regions. The source and drain regions of the first transistor have the same conductivity type as those of the second transistor, and the second transistor has a threshold voltage lower than that of the first transistor. The channel forming region of the second transistor may include a homogeneously doped region, whose conductivity type is the same as the source and drain regions of the second transistor and is different from the channel forming region of the first transistor.

公开(公告)号：US20130234204A1

公开(公告)日：2013-09-12

申请号：US13615968

申请日：2012-09-14

申请人： Myung Gil Kang ,  Changwoo Oh ,  Heedon Jeong ,  Chiwon Cho

发明人： Myung Gil Kang ,  Changwoo Oh ,  Heedon Jeong ,  Chiwon Cho

IPC分类号： H01L29/78

CPC分类号： H01L29/785 ,  H01L21/823821 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851 ,  H01L29/7856

摘要： A Field Effect Transistor (FET) structure may include a fin on a substrate having a first lattice constant and at least two different lattice constant layers on respective different axially oriented surfaces of the fin, wherein the at least two different lattice constant layers each comprise lattice constants that are different than the first lattice constant and each other.

公开(公告)号：US08679910B2

公开(公告)日：2014-03-25

申请号：US13218547

申请日：2011-08-26

申请人： Li Ming ,  Sangpil Sim ,  Kang-ill Seo ,  Changwoo Oh ,  Dongil Bae

发明人： Li Ming ,  Sangpil Sim ,  Kang-ill Seo ,  Changwoo Oh ,  Dongil Bae

IPC分类号： H01L21/00

CPC分类号： H01L21/823807 ,  H01L21/823814

摘要： Provided are methods of fabricating a semiconductor device including a metal oxide semiconductor (MOS) transistor. The methods include forming a gate pattern on a semiconductor substrate. The semiconductor substrate is etched using the gate pattern as an etching mask to form a pair of active trenches spaced apart from each other in the semiconductor substrate. Epitaxial layers are formed in the active trenches, respectively. The respective epitaxial layers are formed by sequentially stacking first and second layers. The first and second layers are formed of a semiconductor layer having a lattice constant greater than the semiconductor substrate, and a composition ratio of the second layer is different from that of the first layer. Semiconductor devices having the first and second layers are also provided.

摘要翻译： 提供制造包括金属氧化物半导体（MOS）晶体管的半导体器件的方法。 所述方法包括在半导体衬底上形成栅极图案。 使用栅极图案作为蚀刻掩模蚀刻半导体衬底，以在半导体衬底中形成彼此间隔开的一对有源沟槽。 分别在有源沟槽中形成外延层。 通过依次层叠第一层和第二层形成各个外延层。 第一层和第二层由具有大于半导体衬底的晶格常数的半导体层形成，并且第二层的组成比不同于第一层的组成比。 还提供具有第一和第二层的半导体器件。

公开(公告)号：US20130249003A1

公开(公告)日：2013-09-26

申请号：US13615671

申请日：2012-09-14

申请人： Changwoo Oh ,  Myung Gil Kang ,  Bomsoo Kim ,  Jongshik Yoon

发明人： Changwoo Oh ,  Myung Gil Kang ,  Bomsoo Kim ,  Jongshik Yoon

IPC分类号： H01L27/12 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L29/1041 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/785

摘要： Field effect transistors are provided. According to the field effect transistor, a source region and a drain region are provided on a substrate and a fin portion is provided to protrude from the substrate. The fin portion connects the source region and the drain region to each other. A gate electrode pattern is disposed on the fin portion and extends to cross over the fin portion. A gate dielectric layer is disposed between the fin portion and the gate electrode pattern. A semiconductor layer is disposed between the fm portion and the gate dielectric layer. The semiconductor layer and the fin portion have dopant-concentrations different from each other, respectively.

摘要翻译： 提供场效应晶体管。 根据场效应晶体管，源极区域和漏极区域设置在基板上，并且翅片部分设置成从基板突出。 翅片部分将源极区域和漏极区域彼此连接。 栅极电极图案设置在翅片部分上并且延伸以跨越翅片部分。 栅极介电层设置在鳍部与栅电极图案之间。 在fm部分和栅极电介质层之间设置半导体层。 半导体层和鳍部分别具有彼此不同的掺杂剂浓度。

公开(公告)号：US20130221447A1

公开(公告)日：2013-08-29

申请号：US13754063

申请日：2013-01-30

申请人： Choong-Ho Lee ,  Donggu Yi ,  Seung Chul Lee ,  Hyungsuk Lee ,  Seonah Nam ,  Changwoo Oh ,  Jongwook Lee ,  Song-Yi Han

发明人： Choong-Ho Lee ,  Donggu Yi ,  Seung Chul Lee ,  Hyungsuk Lee ,  Seonah Nam ,  Changwoo Oh ,  Jongwook Lee ,  Song-Yi Han

IPC分类号： H01L27/092

CPC分类号： H01L29/6681 ,  H01L21/02255 ,  H01L21/32053 ,  H01L21/76224 ,  H01L27/092 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： Provided are field effect transistors and methods of fabricating the same. The transistor may include a substrate with an active pattern, the active pattern having a top surface and two sidewalls, a gate electrode proximal to the top surface and the sidewalls of the active pattern and crossing the active pattern, a gate spacer covering a sidewall of the gate electrode, a gate dielectric pattern at a bottom surface of the gate electrode, a source electrode on the active pattern at one side of the gate electrode, a drain electrode on the active pattern at another side of the gate electrode, and silicide patterns on surfaces of the source and drain electrodes, respectively. The gate dielectric pattern includes at least one high-k layer and the gate spacer has a dielectric constant that is smaller than that of the gate dielectric pattern.

公开(公告)号：US09087723B2

公开(公告)日：2015-07-21

申请号：US13754063

申请日：2013-01-30

申请人： Choong-Ho Lee ,  Donggu Yi ,  Seung Chul Lee ,  Hyungsuk Lee ,  Seonah Nam ,  Changwoo Oh ,  Jongwook Lee ,  Song-Yi Han

发明人： Choong-Ho Lee ,  Donggu Yi ,  Seung Chul Lee ,  Hyungsuk Lee ,  Seonah Nam ,  Changwoo Oh ,  Jongwook Lee ,  Song-Yi Han

IPC分类号： H01L21/70 ,  H01L27/092 ,  H01L29/66 ,  H01L29/51 ,  H01L29/78

CPC分类号： H01L29/6681 ,  H01L21/02255 ,  H01L21/32053 ,  H01L21/76224 ,  H01L27/092 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： Provided are field effect transistors and methods of fabricating the same. The transistor may include a substrate with an active pattern, the active pattern having a top surface and two sidewalls, a gate electrode proximal to the top surface and the sidewalls of the active pattern and crossing the active pattern, a gate spacer covering a sidewall of the gate electrode, a gate dielectric pattern at a bottom surface of the gate electrode, a source electrode on the active pattern at one side of the gate electrode, a drain electrode on the active pattern at another side of the gate electrode, and silicide patterns on surfaces of the source and drain electrodes, respectively. The gate dielectric pattern includes at least one high-k layer and the gate spacer has a dielectric constant that is smaller than that of the gate dielectric pattern.

摘要翻译： 提供场效应晶体管及其制造方法。 晶体管可以包括具有有源图案的衬底，有源图案具有顶表面和两个侧壁，靠近顶表面的栅极电极和有源图案的侧壁并与有源图案交叉，栅极间隔件覆盖侧壁 栅极电极，栅电极的底面的栅极电介质图案，位于栅电极一侧的有源图案上的源电极，栅电极另一侧的有源图案上的漏电极，以及硅化物图案 分别在源电极和漏电极的表面上。 栅极电介质图案包括至少一个高k层，并且栅极间隔物的介电常数小于栅极电介质图案的介电常数。

公开(公告)号：US08941155B2

公开(公告)日：2015-01-27

申请号：US13615968

申请日：2012-09-14

申请人： Myung Gil Kang ,  Changwoo Oh ,  Heedon Jeong ,  Chiwon Cho

发明人： Myung Gil Kang ,  Changwoo Oh ,  Heedon Jeong ,  Chiwon Cho

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L21/823821 ,  H01L29/1054 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851 ,  H01L29/7856

摘要： A Field Effect Transistor (FET) structure may include a fin on a substrate having a first lattice constant and at least two different lattice constant layers on respective different axially oriented surfaces of the fin, wherein the at least two different lattice constant layers each comprise lattice constants that are different than the first lattice constant and each other.

摘要翻译： 场效应晶体管（FET）结构可以包括在鳍的相应不同轴向取向表面上的具有第一晶格常数和至少两个不同晶格常数层的衬底上的鳍，其中所述至少两个不同的晶格常数层各自包括晶格 与第一晶格常数不同的常数和彼此。