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    MULTI-FILM STACK ETCHING WITH POLYMER PASSIVATION OF AN OVERLYING ETCHED LAYER
    1.
    发明申请
    MULTI-FILM STACK ETCHING WITH POLYMER PASSIVATION OF AN OVERLYING ETCHED LAYER 失效
    多层蚀刻层的聚合物钝化的多层堆叠蚀刻

    公开(公告)号：US20110045672A1

    公开(公告)日：2011-02-24

    申请号：US12860672

    申请日：2010-08-20

    申请人： Sunil Srinivasan ,  Jinhan Choi ,  Anisul H. Khan

    发明人： Sunil Srinivasan ,  Jinhan Choi ,  Anisul H. Khan

    IPC分类号： H01L21/3065 ,  C23F1/08

    CPC分类号： C23F4/00 ,  H01J37/32449 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/67069 ,  H01L27/0688

    摘要： A method and apparatus for plasma etching a workpiece, such as a semiconductor wafer, including a thin film stack having a top film disposed over a bottom film with an intervening middle film there between. Etch selectivity between the top and bottom films may be as low as between 1:1 and 2:1 and a first carbon-lean gas chemistry is used to etch through the top film, a second carbon-lean gas chemistry is used to etch through the middle film, and the bottom film is etched through by alternating between depositing a polymer passivation on the top film using a carbon-rich gas chemistry and an etching of the bottom film with a third carbon-lean gas chemistry, which may be the same as the first carbon-lean gas chemistry.

    摘要翻译： 一种用于等离子体蚀刻诸如半导体晶片的工件的方法和装置，包括具有设置在底部膜上的顶部薄膜的薄膜叠层，其间具有介于其间的中间膜。 顶部和底部薄膜之间的蚀刻选择性可以低至1：1和2：1之间，并且使用第一种贫碳气体化学品来蚀刻顶部薄膜，第二种贫碳气体化学物质用于蚀刻 通过使用富碳气体化学沉积顶部膜上的聚合物钝化物和用可能相同的第三种贫碳气体化学物质对底部膜进行蚀刻，交替地蚀刻中间膜和底部膜 作为第一个贫碳气体化学。

    Multi-film stack etching with polymer passivation of an overlying etched layer
    2.
    发明授权
    Multi-film stack etching with polymer passivation of an overlying etched layer 失效
    多层叠层蚀刻与上覆蚀刻层的聚合物钝化

    公开(公告)号：US08747684B2

    公开(公告)日：2014-06-10

    申请号：US12860672

    申请日：2010-08-20

    申请人： Sunil Srinivasan ,  Jinhan Choi ,  Anisul H. Khan

    发明人： Sunil Srinivasan ,  Jinhan Choi ,  Anisul H. Khan

    IPC分类号： B44C1/22

    CPC分类号： C23F4/00 ,  H01J37/32449 ,  H01L21/32136 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/67069 ,  H01L27/0688

    摘要： A method and apparatus for plasma etching a workpiece, such as a semiconductor wafer, including a thin film stack having a top film disposed over a bottom film with an intervening middle film there between. Etch selectivity between the top and bottom films may be as low as between 1:1 and 2:1 and a first carbon-lean gas chemistry is used to etch through the top film, a second carbon-lean gas chemistry is used to etch through the middle film, and the bottom film is etched through by alternating between depositing a polymer passivation on the top film using a carbon-rich gas chemistry and an etching of the bottom film with a third carbon-lean gas chemistry, which may be the same as the first carbon-lean gas chemistry.

    摘要翻译： 一种用于等离子体蚀刻诸如半导体晶片的工件的方法和装置，包括具有设置在底部膜上的顶部薄膜的薄膜叠层，其间具有介于其间的中间膜。 顶部和底部薄膜之间的蚀刻选择性可以低至1：1和2：1之间，并且使用第一种贫碳气体化学品来蚀刻顶部薄膜，第二种贫碳气体化学物质用于蚀刻 通过使用富碳气体化学沉积顶部膜上的聚合物钝化物和用可能相同的第三种贫碳气体化学物质对底部膜进行蚀刻，交替地蚀刻中间膜和底部膜 作为第一个贫碳气体化学。

    Shallow trench isolation etch process
    3.
    发明授权
    Shallow trench isolation etch process 失效
    浅沟槽隔离蚀刻工艺

    公开(公告)号：US08133817B2

    公开(公告)日：2012-03-13

    申请号：US12325220

    申请日：2008-11-30

    申请人： Hiroki Sasano ,  Meihua Shen ,  Radhika Mani ,  Sunil Srinivasan ,  Daehee Weon ,  Nicolas Gani ,  Shashank Deshmukh ,  Anisul Khan

    发明人： Hiroki Sasano ,  Meihua Shen ,  Radhika Mani ,  Sunil Srinivasan ,  Daehee Weon ,  Nicolas Gani ,  Shashank Deshmukh ,  Anisul Khan

    IPC分类号： H01L21/302

    CPC分类号： H01L21/3065 ,  H01L21/76224

    摘要： Methods for fabricating one or more shallow trench isolation (STI) structures are provided herein. In some embodiments, a method for fabricating one or more shallow trench isolation (STI) structures may include providing a substrate having a patterned mask layer disposed thereon to define one or more STI structures. The substrate may be etched using a plasma formed from a process gas mixture to form one or more STI structures on the substrate, wherein the process gas mixture comprises a fluorine-containing gas and either a fluorocarbon-containing gas or a hydrofluorocarbon-containing gas.

    摘要翻译： 本文提供了制造一个或多个浅沟槽隔离（STI）结构的方法。 在一些实施例中，用于制造一个或多个浅沟槽隔离（STI）结构的方法可以包括提供具有设置在其上以限定一个或多个STI结构的图案化掩模层的衬底。 可以使用由工艺气体混合物形成的等离子体来蚀刻衬底，以在衬底上形成一个或多个STI结构，其中工艺气体混合物包含含氟气体和含氟烃气体或含氢氟烃的气体。

    Notch-Free Etching of High Aspect SOI Structures Using A Time Division Multiplex Process and RF Bias Modulation
    4.
    发明申请
    Notch-Free Etching of High Aspect SOI Structures Using A Time Division Multiplex Process and RF Bias Modulation 审中-公开
    使用时分复用过程和RF偏置调制的高截面SOI结构的无槽蚀刻

    公开(公告)号：US20070175856A1

    公开(公告)日：2007-08-02

    申请号：US11681004

    申请日：2007-04-16

    申请人： David Johnson ,  Russell Westerman ,  Sunil Srinivasan

    发明人： David Johnson ,  Russell Westerman ,  Sunil Srinivasan

    IPC分类号： C23C16/00 ,  C23F1/00 ,  H01L21/306

    CPC分类号： H01L21/30655 ,  H01L21/76283

    摘要： The present invention provides a method and an apparatus for reducing, or eliminating, the notching observed in the creation of SOI structures on a substrate when plasma etching through an alternating deposition/etch process by modulating the RF bias that is applied to the cathode. Modulation of the bias voltage to the cathode is accomplished either discretely, between at least two frequencies, or continuously during the alternating deposition/etch process.

    摘要翻译： 本发明提供了一种用于减少或消除在通过调制施加到阴极的RF偏压的交替沉积/蚀刻工艺的等离子体蚀刻时在衬底上产生SOI结构时观察到的凹口的方法和装置。 对阴极的偏置电压的调制在离散地，至少两个频率之间或在交替沉积/蚀刻过程期间连续地实现。

    SHALLOW TRENCH ISOLATION ETCH PROCESS
    5.
    发明申请
    SHALLOW TRENCH ISOLATION ETCH PROCESS 失效
    SHOWOW TRENCH隔离蚀刻工艺

    公开(公告)号：US20090170333A1

    公开(公告)日：2009-07-02

    申请号：US12325220

    申请日：2008-11-30

    申请人： Hiroki Sasano ,  Meihua Shen ,  Radhika Mani ,  Sunil Srinivasan ,  Daehee Weon ,  Nicolas Gani ,  Shashank Deshmukh ,  Anisul Khan

    发明人： Hiroki Sasano ,  Meihua Shen ,  Radhika Mani ,  Sunil Srinivasan ,  Daehee Weon ,  Nicolas Gani ,  Shashank Deshmukh ,  Anisul Khan

    IPC分类号： H01L21/302

    CPC分类号： H01L21/3065 ,  H01L21/76224

    摘要： Methods for fabricating one or more shallow trench isolation (STI) structures are provided herein. In some embodiments, a method for fabricating one or more shallow trench isolation (STI) structures may include providing a substrate having a patterned mask layer disposed thereon to define one or more STI structures. The substrate may be etched using a plasma formed from a process gas mixture to form one or more STI structures on the substrate, wherein the process gas mixture comprises a fluorine-containing gas and either a fluorocarbon-containing gas or a hydrofluorocarbon-containing gas.

    摘要翻译： 本文提供了制造一个或多个浅沟槽隔离（STI）结构的方法。 在一些实施例中，用于制造一个或多个浅沟槽隔离（STI）结构的方法可以包括提供具有设置在其上以限定一个或多个STI结构的图案化掩模层的衬底。 可以使用由工艺气体混合物形成的等离子体来蚀刻衬底，以在衬底上形成一个或多个STI结构，其中工艺气体混合物包含含氟气体和含氟烃气体或含氢氟烃的气体。

    Method to Minimize CD Etch Bias
    6.
    发明申请
    Method to Minimize CD Etch Bias 有权
    减少CD蚀刻偏差的方法

    公开(公告)号：US20080035606A1

    公开(公告)日：2008-02-14

    申请号：US11834299

    申请日：2007-08-06

    申请人： Jason Plumhoff ,  Sunil Srinivasan ,  David Johnson ,  Russell Westerman

    发明人： Jason Plumhoff ,  Sunil Srinivasan ,  David Johnson ,  Russell Westerman

    IPC分类号： G01R31/00

    CPC分类号： C23F4/00 ,  G03F1/54 ,  G03F1/80

    摘要： The present invention provides a method for improving the critical dimension performance during a plasma etching process of a photolithographic substrate having a thin film. A passivation film is deposited onto the photolithographic substrate using a first set of process conditions. The deposited film is etched from the photolithographic substrate using a second set of process conditions. An exposed surface of the photolithographic substrate is etched using a third set of process conditions. During the plasma processing of the photolithographic substrate, the critical dimension performance of the photolithographic substrate is monitored to insure that the target uniformity and feature widths are obtained by adjusting the deposition and etch plasma processing of the photolithographic substrate.

    摘要翻译： 本发明提供了一种在具有薄膜的光刻基片的等离子体蚀刻工艺中提高临界尺寸性能的方法。 使用第一组工艺条件将钝化膜沉积在光刻基板上。 使用第二组工艺条件从光刻基板蚀刻沉积的膜。 使用第三组工艺条件蚀刻光刻基片的暴露表面。 在光刻基板的等离子体处理期间，监测光刻基板的临界尺寸性能，以确保通过调整光刻基板的沉积和蚀刻等离子体处理来获得目标均匀性和特征宽度。

    Method to minimize CD etch bias
    7.
    发明授权
    Method to minimize CD etch bias 有权
    减少CD蚀刻偏差的方法

    公开(公告)号：US08187483B2

    公开(公告)日：2012-05-29

    申请号：US11834299

    申请日：2007-08-06

    申请人： Jason Plumhoff ,  Sunil Srinivasan ,  David Johnson ,  Russell Westerman

    发明人： Jason Plumhoff ,  Sunil Srinivasan ,  David Johnson ,  Russell Westerman

    IPC分类号： G01L21/00 ,  H01L21/00

    CPC分类号： C23F4/00 ,  G03F1/54 ,  G03F1/80

    摘要： The present invention provides a method for improving the critical dimension performance during a plasma etching process of a photolithographic substrate having a thin film. A passivation film is deposited onto the photolithographic substrate using a first set of process conditions. The deposited film is etched from the photolithographic substrate using a second set of process conditions. An exposed surface of the photolithographic substrate is etched using a third set of process conditions. During the plasma processing of the photolithographic substrate, the critical dimension performance of the photolithographic substrate is monitored to insure that the target uniformity and feature widths are obtained by adjusting the deposition and etch plasma processing of the photolithographic substrate.

    摘要翻译： 本发明提供了一种在具有薄膜的光刻基片的等离子体蚀刻工艺中提高临界尺寸性能的方法。 使用第一组工艺条件将钝化膜沉积在光刻基板上。 使用第二组工艺条件从光刻基板蚀刻沉积的膜。 使用第三组工艺条件蚀刻光刻基片的暴露表面。 在光刻基板的等离子体处理期间，监测光刻基板的临界尺寸性能，以确保通过调整光刻基板的沉积和蚀刻等离子体处理来获得目标均匀性和特征宽度。