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    Programmable logic device having an embedded differential clock tree
    1.
    发明申请
    Programmable logic device having an embedded differential clock tree 有权
    具有嵌入式差分时钟树的可编程逻辑器件

    公开(公告)号：US20050242866A1

    公开(公告)日：2005-11-03

    申请号：US10837009

    申请日：2004-04-30

    申请人： Vasisht Vadi ,  Steven Young ,  Atul Ghia ,  Adebabay Bekele ,  Suresh Menon

    发明人： Vasisht Vadi ,  Steven Young ,  Atul Ghia ,  Adebabay Bekele ,  Suresh Menon

    IPC分类号： G06F1/10 ,  H03F3/45 ,  H03K5/15 ,  H03K19/177

    CPC分类号： G06F1/10 ,  H03K5/15013 ,  H03K19/1774 ,  H03K19/17784 ,  H03K19/17796

    摘要： A clock distribution network having: a backbone clock signal line configured to provide a differential clock signal; multiple branches coupled to the backbone clock signal line for distributing the differential clock signal to multiple programmable function elements; a first leaf node coupled to a first branch, where the first leaf node is configured to provide the differential clock signal to a first programmable function element; and a second leaf node coupled to a second branch, where the second leaf node is configured to provide a single ended clock signal derived from the differential clock signal to a second programmable function element.

    摘要翻译： 一种时钟分配网络，具有：骨干时钟信号线，被配置为提供差分时钟信号; 多个分支耦合到主干时钟信号线，用于将差分时钟信号分配给多个可编程功能元件; 耦合到第一分支的第一叶节点，其中所述第一叶节点被配置为将所述差分时钟信号提供给第一可编程功能元件; 以及耦合到第二分支的第二叶节点，其中所述第二叶节点被配置为将从所述差分时钟信号导出的单端时钟信号提供给第二可编程功能元件。

    Dual port voltage controlled emitter coupled multivibrator
    4.
    发明授权
    Dual port voltage controlled emitter coupled multivibrator 失效
    双端口压控发射极耦合多谐振荡器

    公开(公告)号：US4884042A

    公开(公告)日：1989-11-28

    申请号：US311493

    申请日：1989-02-15

    申请人： Suresh Menon ,  Enjeti Murthi

    发明人： Suresh Menon ,  Enjeti Murthi

    IPC分类号： H03C3/00 ,  H03K3/011 ,  H03K3/282 ,  H03L7/099

    CPC分类号： H03K3/011 ,  H03K3/2821

    摘要： A voltage controlled oscillator includes an emitter coupled multivibrator in which a capacitor determines the frequency of oscillation along with a pair of load resistors and a pair of current sources. A differential amplifier is coupled to operate in parallel with the mutlivibrator and its tail current is operated differentially, with respect to the currents in the pair of sources, in response to the input voltage at a first modulation input port. Thus, a constant current flows in the multivibrator loads even when the frequency is modulated. A second input port is coupled to vary the tail current in the differential amplifier to comprise a dual port control of the voltage controlled oscillator. The circuit can be operated at a relatively low supply voltage and can be temperature compensated. Furthermore, the input ports can include circuitry having a logarithmic response for digital signaling processing.

    Differential clock tree in an integrated circuit
    8.
    发明申请
    Differential clock tree in an integrated circuit 有权
    差分时钟树在集成电路中

    公开(公告)号：US20070013428A1

    公开(公告)日：2007-01-18

    申请号：US11511779

    申请日：2006-08-29

    申请人： Vasisht Vadi ,  Steven Young ,  Atul Ghia ,  Adebabay Bekele ,  Suresh Menon

    发明人： Vasisht Vadi ,  Steven Young ,  Atul Ghia ,  Adebabay Bekele ,  Suresh Menon

    IPC分类号： G06F1/04

    CPC分类号： G06F1/10 ,  H03K5/2481

    摘要： A clock distribution network having: a main trunk configured to provide a differential clock signal; a plurality of branches coupled to the main trunk for distributing the differential clock signal to a plurality of circuit elements on the integrated circuit; and a plurality of switches coupling the main trunk to the plurality of branches.

    摘要翻译： 一种时钟分配网络，具有：主干线，被配置为提供差分时钟信号; 耦合到所述主干线的多个分支，用于将所述差分时钟信号分配给所述集成电路上的多个电路元件; 以及将主干线连接到多个分支的多个开关。