公开(公告)号：US4270116A

公开(公告)日：1981-05-26

申请号：US69347

申请日：1979-08-24

申请人： Yoshichika Ichimiya ,  Tsuneta Sudo ,  Hiromi Maruyama ,  Shigeru Sugamori ,  Susumu Sumida ,  Masao Shimizu ,  Toshiaki Wakita

发明人： Yoshichika Ichimiya ,  Tsuneta Sudo ,  Hiromi Maruyama ,  Shigeru Sugamori ,  Susumu Sumida ,  Masao Shimizu ,  Toshiaki Wakita

IPC分类号： G01R31/28 ,  G06F7/02 ,  G06F7/04 ,  G06F11/22

CPC分类号： G06F7/02

摘要： Reference logical data is spatially divided by a data dividing circuit for each time slot, and the divided data are converted into data, each having a continuous effective period. The divided and converted reference data and input logical data are compared by comparators to detect whether or not they are coincident with each other. A clock signal for determining the timing of comparison is also divided by a clock signal dividing circuit into n clock signals which are displaced one time slot apart in phase and occurring with a period of n time slots. By these divided clock signals those of the outputs from the comparators corresponding thereto are taken out from a comparison output circuit.

摘要翻译： 参考逻辑数据由每个时隙的数据分割电路在空间上划分，并且分割的数据被转换成数据，每个数据具有连续的有效周期。 通过比较器比较分割和转换的参考数据和输入逻辑数据，以检测它们是否彼此一致。 用于确定比较定时的时钟信号也被时钟信号分频电路划分为n个时钟信号，这些n个时钟信号相移一个时隙并且以n个时隙的周期发生。 通过这些分开的时钟信号，从比较输出电路中取出与其相对应的比较器的输出。

公开(公告)号：US4310802A

公开(公告)日：1982-01-12

申请号：US69348

申请日：1979-08-24

申请人： Yoshichika Ichimiya ,  Tsuneta Sudo ,  Hiromi Maruyama ,  Shigeru Sugamori ,  Susumu Sumida ,  Takashi Tokuno

发明人： Yoshichika Ichimiya ,  Tsuneta Sudo ,  Hiromi Maruyama ,  Shigeru Sugamori ,  Susumu Sumida ,  Takashi Tokuno

IPC分类号： G06F11/22 ,  G01R31/3183 ,  G01R31/319 ,  G06F1/06 ,  H03K5/135 ,  H03K5/156 ,  H03K5/22

CPC分类号： G01R31/31922 ,  H03K5/156 ,  G01R31/31928

摘要： Input logical data is sequentially divided by a data dividing circuit for each time slot into n data trains, of which each data block has an n time slot length. A clock signal which can be arbitrarily timed, is divided by a clock dividing circuit into a n clock signals which are displaced one time slot apart in phase and which occur with a period of n time slots. In a logical circuit, the divided clock signals are controlled by the divided data trains corresponding thereto, and the controlled clock signals are time multiplexed by a multiplexing circuit, whereby output data with which the input logical data has been timed by the clock signal is obtained.

摘要翻译： 输入逻辑数据由每个时隙的数据分割电路顺序划分成n个数据列，每个数据块具有n个时隙长度。 可以任意定时的时钟信号由时钟分频电路划分成n个时钟信号，这些时钟信号在相位上分离一个时隙并且以n个时隙的周期发生。 在逻辑电路中，划分的时钟信号由对应的分割数据串进行控制，并且受控时钟信号由复用电路进行时间复用，从而获得输入逻辑数据已被时钟信号定时的输出数据 。

公开(公告)号：US07089135B2

公开(公告)日：2006-08-08

申请号：US10150777

申请日：2002-05-20

申请人： Rochit Rajsuman ,  Shigeru Sugamori ,  Robert F. Sauer ,  Hiroaki Yamoto ,  James Alan Turnquist ,  Bruce R. Parnas ,  Anthony Le

发明人： Rochit Rajsuman ,  Shigeru Sugamori ,  Robert F. Sauer ,  Hiroaki Yamoto ,  James Alan Turnquist ,  Bruce R. Parnas ,  Anthony Le

IPC分类号： G01R31/00

CPC分类号： G01R31/31813 ,  G01R31/318307 ,  G01R31/318342 ,  G01R31/31917 ,  G01R31/31919 ,  G01R31/31928

摘要： An event based test system for testing an IC device under test (DUT) designed under an automatic electronic design (EDA) environment. The event based test system includes an event memory for storing event data derived directly from simulation of design data for an intended IC in the EDA environment where the event data to denote each event is formed with time index indicating a time length from a predetermined point and an event type indicating a type of change at an event, an event generation unit for generating test vectors based on the event data where waveform of each vector is determined by the event type and a timing of the waveform is determined by accumulating the time index of previous events, and means for supplying test vectors to the DUT and evaluating response outputs of the DUT at predetermined timings.

摘要翻译： 一种基于事件的测试系统，用于测试在自动电子设计（EDA）环境下设计的待测IC器件（DUT）。 基于事件的测试系统包括事件存储器，用于存储在EDA环境中直接从对于期望的IC的设计数据的模拟得到的事件数据，其中表示每个事件的事件数据形成有指示来自预定点的时间长度的时间索引， 指示事件变化类型的事件类型，用于根据事件数据生成测试矢量的事件生成单元，其中由事件类型确定每个矢量的波形，并且通过累积波形的时间指数来确定波形的定时 以前的事件，以及用于向DUT提供测试向量并在预定定时评估DUT的响应输出的装置。

公开(公告)号：US06331770B1

公开(公告)日：2001-12-18

申请号：US09547753

申请日：2000-04-12

申请人： Shigeru Sugamori

发明人： Shigeru Sugamori

IPC分类号： G01R700

CPC分类号： G01R31/31724 ,  G01R31/3167 ,  G01R31/3187 ,  G01R31/31905 ,  G01R31/31921 ,  G01R31/31922

摘要： A semiconductor test system for testing semiconductor devices, and particularly, to a semiconductor test system having a plurality of different types of tester modules in a main frame and a measurement module unique to the device under test in a test fixture, thereby achieving a low cost and application specific test system. The semiconductor test system includes two or more tester modules whose performances are different from one another, a test system main frame to accommodate a combination of two or more tester modules, a test fixture provided on the main frame for electrically connecting the tester modules and a device under test, a measurement module provided in the test fixture for converting signals between the device under test and the tester module depending on the function of the device under test, and a host computer for controlling an overall operation of the test system by communicating with the tester modules through a tester bus.

摘要翻译： 一种用于测试半导体器件的半导体测试系统，特别是涉及一种半导体测试系统，该半导体测试系统在主框架中具有多个不同类型的测试器模块，以及在测试夹具中对被测器件特有的测量模块，从而实现了低成本 和应用程序特定的测试系统。 半导体测试系统包括两个或更多个性能彼此不同的测试器模块，用于容纳两个或更多个测试器模块的组合的测试系统主框架，设置在主框架上用于电连接测试器模块的测试夹具和 被测设备，设置在测试夹具中的测量模块，用于根据所测试的设备的功能，在被测设备和测试器模块之间转换信号;以及主计算机，用于通过与测试系统的通信进行通信来控制测试系统的整体操作 测试仪模块通过测试仪总线。

公开(公告)号：US4497056A

公开(公告)日：1985-01-29

申请号：US407872

申请日：1982-08-13

申请人： Shigeru Sugamori

发明人： Shigeru Sugamori

IPC分类号： G01R31/28 ,  G01R31/3183 ,  G01R31/319 ,  H01L21/66

CPC分类号： G01R31/3191

摘要： An IC tester supplies test pattern signal to an IC being tested and compares response signals therefrom with an expected-value pattern signal to determine whether the IC is acceptable or not. During the test, the IC being tested is severed by a separator means from the drivers, for producing the test pattern signals with a timing signal generator set in a condition for generating reference signals. The reference signals and the outputs from the drivers are compared for phase by a phase comparator means. Variable delay means inserted in the paths of the test pattern signal are adjusted by the result of the comparison to suppress skews between the paths of the test pattern signals. Skews in strobe signals, which serve to determine the logic levels of the response signals output from the IC being tested, are also suppressed.

摘要翻译： IC测试器将测试图形信号提供给正在测试的IC，并将其中的响应信号与预期值图案信号进行比较，以确定IC是否可接受。 在测试期间，被测试的IC被来自驱动器的分离器装置切断，以便在产生参考信号的条件下用定时信号发生器产生测试图形信号。 驱动器的参考信号和输出通过相位比较器进行相位比较。 通过比较结果调整插入在测试图形信号的路径中的可变延迟装置，以抑制测试图形信号的路径之间的偏差。 用于确定从所测试的IC输出的响应信号的逻辑电平的选通信号中的偏移也被抑制。

公开(公告)号：US07596730B2

公开(公告)日：2009-09-29

申请号：US11394814

申请日：2006-03-31

申请人： Yuya Watanabe ,  Shigeru Sugamori ,  Hiroaki Yamoto

发明人： Yuya Watanabe ,  Shigeru Sugamori ,  Hiroaki Yamoto

IPC分类号： G01R31/28

CPC分类号： G01R31/31919

摘要： A test method for testing a device under test by using an event tester is provided. The test method includes: receiving a test signal generated by the event tester and applied to the device under test and sequentially writing the same to a memory; reading sequentially the written test signal from the memory at the speed higher than that of the test signal generated by the event tester and applying the same to the device under test; acquiring the output signal outputted from the device under test in response to the applied test signal and sequentially writing the same at the speed higher than that of the test signal generated by the event tester; sequentially reading the written output signal from the memory and transmitting the same at the speed lower than that of the output signal outputted from the device under test; and determining pass/fail of the transmitted output signal by the event tester.

摘要翻译： 提供了一种通过使用事件测试仪测试被测器件的测试方法。 测试方法包括：接收由事件测试器生成的测试信号，并将其应用于被测设备，并将其顺序写入存储器; 以比由事件测试仪产生的测试信号高的速度从存储器顺序读取写入的测试信号，并将其应用于被测器件; 响应于所施加的测试信号获取从被测设备输出的输出信号，并以比由事件测试仪产生的测试信号高的速度顺序写入; 从存储器顺序读取写入的输出信号，并以比从被测器件输出的输出信号的速度低的速度传输; 并通过事件测试器确定发送的输出信号的通过/失败。

公开(公告)号：US20070234146A1

公开(公告)日：2007-10-04

申请号：US11394814

申请日：2006-03-31

申请人： Yuya Watanabe ,  Shigeru Sugamori ,  Hiroaki Yamoto

发明人： Yuya Watanabe ,  Shigeru Sugamori ,  Hiroaki Yamoto

IPC分类号： G01R31/28

CPC分类号： G01R31/31919

摘要： A test method for testing a device under test by using an event tester is provided. The test method includes: receiving a test signal generated by the event tester and applied to the device under test and sequentially writing the same to a memory ; reading sequentially the written test signal from the memory at the speed higher than that of the test signal generated by the event tester and applying the same to the device under test; acquiring the output signal outputted from the device under test in response to the applied test signal and sequentially writing the same at the speed higher than that of the test signal generated by the event tester; sequentially reading the written output signal from the memory and transmitting the same at the speed lower than that of the output signal outputted from the device under test; and determining pass/fail of the transmitted output signal by the event tester.

摘要翻译： 提供了一种通过使用事件测试仪测试被测器件的测试方法。 测试方法包括：接收由事件测试器生成的测试信号，并将其应用于被测设备，并将其顺序写入存储器; 以比由事件测试仪产生的测试信号高的速度从存储器顺序读取写入的测试信号，并将其应用于被测器件; 响应于所施加的测试信号获取从被测设备输出的输出信号，并以比由事件测试仪产生的测试信号高的速度顺序写入; 从存储器顺序读取写入的输出信号，并以比从被测器件输出的输出信号的速度低的速度传输; 并通过事件测试器确定发送的输出信号的通过/失败。

公开(公告)号：US06678643B1

公开(公告)日：2004-01-13

申请号：US09340371

申请日：1999-06-28

申请人： James Alan Turnquist ,  Shigeru Sugamori ,  Hiroaki Yamoto

发明人： James Alan Turnquist ,  Shigeru Sugamori ,  Hiroaki Yamoto

IPC分类号： G06F1100

CPC分类号： G01R31/318314 ,  G01R31/318307 ,  G01R31/318342

摘要： A semiconductor test system which generates a test pattern produced based on data resultant to device logic simulation performed on a computer for an LSI device designed in an electronic design automation (EDA) environment, tests the LSI device, and feedbacks the test results to the EDA environment. The semiconductor test system includes an event file for storing event data obtained by executing device logic simulation in a design stage of an LSI device under test; an event memory for storing the event data from the event file relative to timings; means for generating a test pattern by directly using the event data from the event memory and applying the test pattern to the LSI device under test; a result data file for evaluating a response output of the LSI device under test and storing resultant evaluation data; and means for evaluating design of the LSI device based on the data stored in the result data file.

摘要翻译： 一种半导体测试系统，其生成基于在用于在电子设计自动化（EDA）环境中设计的LSI设备的计算机上执行的器件逻辑模拟的数据生成的测试图案，测试LSI器件，并将测试结果反馈给EDA 环境。 半导体测试系统包括用于存储通过在被测LSI的设计阶段执行设备逻辑仿真获得的事件数据的事件文件; 事件存储器，用于存储事件文件相对于定时的事件数据; 用于通过直接使用来自事件存储器的事件数据并将测试图案应用于被测试的LSI设备来产生测试图案的装置; 用于评估所测试的LSI设备的响应输出并存储所得到的评估数据的结果数据文件; 以及用于基于存储在结果数据文件中的数据来评估LSI设备的设计的装置。

公开(公告)号：US06567941B1

公开(公告)日：2003-05-20

申请号：US09547752

申请日：2000-04-12

申请人： James Alan Turnquist ,  Rochit Rajsuman ,  Shigeru Sugamori

发明人： James Alan Turnquist ,  Rochit Rajsuman ,  Shigeru Sugamori

IPC分类号： G01R3128

CPC分类号： G11C29/56 ,  G01R31/3191 ,  G01R31/31937

摘要： An event based test system has a cost effective, error free, secure and simple way of managing the calibration data for all of the pin cards used therein. The test system has a large number of test channels for testing a semiconductor device under test (DUT) by applying test patterns to device pins of the DUT through the test channels and examining response outputs of the DUT. The test system includes a plurality of pin cards, each having a plurality of pin units therein to establish a part of the test channels, a non-volatile memory provided within each pin card for storing calibration data for compensating error factors involved in the pin units mounted in the corresponding pin card, and a microprocessor provided within each pin card for managing the calibration data and executing the calibration procedure for all of the pin units in the corresponding pin card, and wherein each pin unit is configured as an event tester in which a test, pattern or a strobe signal is directly generated based on event data stored in an event memory which define any changes from a previous event with reference to a time difference therefrom.

摘要翻译： 基于事件的测试系统具有成本效益，无错误，安全和简单的方式来管理其中使用的所有针卡的校准数据。 测试系统具有大量用于测试被测半导体器件（DUT）的测试通道，通过测试通道将测试模式应用于DUT的器件引脚并检查DUT的响应输出。 测试系统包括多个针卡，每个针卡在其中具有多个针单元以建立测试通道的一部分;提供在每个针卡内的非易失性存储器，用于存储用于补偿引脚单元中涉及的误差因素的校准数据 安装在相应的针脚卡中的微处理器，以及设置在每个针卡内的微处理器，用于管理校准数据并对相应的针卡中的所有针单元执行校准程序，并且其中每个针单元配置为事件测试器，其中 基于存储在事件存储器中的事件数据直接生成测试，模式或选通信号，所述事件数据定义了与先前事件相关的时间差的任何变化。

公开(公告)号：US06651204B1

公开(公告)日：2003-11-18

申请号：US09585831

申请日：2000-06-01

申请人： Rochit Rajsuman ,  Shigeru Sugamori ,  Hiroaki Yamoto

发明人： Rochit Rajsuman ,  Shigeru Sugamori ,  Hiroaki Yamoto

IPC分类号： G01R3128

CPC分类号： G01R31/31915

摘要： An event based test system has a modular architecture for simultaneously testing a plurality of semiconductor devices (DUT) including memory and logic devices. The test system detects functional faults as well as physical faults in the DUT. The test system includes two or more tester modules each having a plurality of pin units, a main frame for accommodating the two or more tester modules, a test fixture for electrically connecting the tester modules and the DUT, a host computer for controlling an overall operation of the test system, and a data storage for storing a library of algorithmic test patterns and software tools for producing memory test patterns for testing memories. Memory test algorithm and information regarding the design and configuration of the memories to be tested are specified prior to the memory testing.

摘要翻译： 基于事件的测试系统具有用于同时测试包括存储器和逻辑器件的多个半导体器件（DUT）的模块化架构。 测试系统检测DUT中的功能故障以及物理故障。 测试系统包括两个或多个测试器模块，每个测试模块具有多个引脚单元，用于容纳两个或更多个测试器模块的主框架，用于电连接测试器模块和DUT的测试夹具，用于控制整个操作的主计算机 的测试系统，以及用于存储用于产生用于测试存储器的存储器测试模式的算法测试模式和软件工具库的数据存储器。 存储器测试算法和有关要测试的存储器的设计和配置的信息在存储器测试之前被指定。